TinyLogic ULP-A Dual 2-Input NAND Gate

The NC7WP00 is a dual 2−input NAND gate in tiny footprint packages. The device is designed to operate for VCC = 0.9 V to 3.6 V. Features • Designed for 0.9 V to 3.6 V VCC Operation • 2.1 ns tPD at 3.3 V (Typ) • Inputs/Outputs Over−Voltage Tolerant up to 3.6 V • IOFF Supports Partial Power

文件：533.04 Kbytes 页数：9 Pages

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TinyLogic ULP Dual 2-Input NAND Gate

文件：192.08 Kbytes 页数：9 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

ULP Dual 2-Input NAND Gate

文件：292.51 Kbytes 页数：11 Pages

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TinyLogic ULP 双通道双输入 NAND 门

NC7WP00是一款双通道2输入NAND门，属于飞兆TinyLogic®中的超低功耗(ULP)系列。 适用于电池使用寿命至关重要的应用，此产品专为0.9V至3.6V VCC工作范围内的超低功耗而设计。 内部电路由最小量的反相器层级组成（包括输出缓冲器），以实现超低静态和动态功率。 NC7WP00专为优化功耗和速度而设计，采用先进的CMOS技术制造，在实现高速运行的同时又能保持极低的CMOS功耗。 •节省空间的US8封装\n•超小型MicroPak™ 无铅封装\n•0.9V至3.6V VCC电源操作范围\n•VCC为0.9 V至3.6 V时，耐过压I/O为3.6 V\n•tPD3 ns（典型值），3.0 V至3.6 V VCC4 ns（典型值），2.3 V至2.7 V VCC5 ns（典型值），1.65 V至1.95 V VCC6 ns（典型值），1.40 V至1.60 V VCC9 ns（典型值），1.10 V至1.30 V VCC24 ns（典型值），0.90 V VCC\n•断电高阻抗输入和输出\n•静态驱动(IOH/IOL)3.00V VCC时±2.6 mA、2.30V VCC时;

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TinyLogic ULP-A Dual 2-Input NAND Gate

The NC7WP00 is a dual 2−input NAND gate in tiny footprint packages. The device is designed to operate for VCC = 0.9 V to 3.6 V. Features • Designed for 0.9 V to 3.6 V VCC Operation • 2.1 ns tPD at 3.3 V (Typ) • Inputs/Outputs Over−Voltage Tolerant up to 3.6 V • IOFF Supports Partial Power

文件：533.04 Kbytes 页数：9 Pages

ONSEMI

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丝印：WP00；Package：US8；TinyLogic ULP-A Dual 2-Input NAND Gate

The NC7WP00 is a dual 2−input NAND gate in tiny footprint packages. The device is designed to operate for VCC = 0.9 V to 3.6 V. Features • Designed for 0.9 V to 3.6 V VCC Operation • 2.1 ns tPD at 3.3 V (Typ) • Inputs/Outputs Over−Voltage Tolerant up to 3.6 V • IOFF Supports Partial Power

文件：533.04 Kbytes 页数：9 Pages

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丝印：Y3；Package：UQFN8；TinyLogic ULP-A Dual 2-Input NAND Gate

The NC7WP00 is a dual 2−input NAND gate in tiny footprint packages. The device is designed to operate for VCC = 0.9 V to 3.6 V. Features • Designed for 0.9 V to 3.6 V VCC Operation • 2.1 ns tPD at 3.3 V (Typ) • Inputs/Outputs Over−Voltage Tolerant up to 3.6 V • IOFF Supports Partial Power

文件：533.04 Kbytes 页数：9 Pages

ONSEMI

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丝印：WP00；Package：MAB08A；ULP Dual 2-Input NAND Gate

文件：292.51 Kbytes 页数：11 Pages

ONSEMI

安森美半导体

TinyLogic ULP Dual 2-Input NAND Gate

文件：192.08 Kbytes 页数：9 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

TinyLogic ULP Dual 2-Input NAND Gate

文件：192.08 Kbytes 页数：9 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司