NB7L11M中文资料Clock / Data Fanout Buffer / Translator, 2.5 V / 3.3 V, with CML Outputs and Internal Termination数据手册ONSEMI规格书

描述 Description

The NB7L11M is a differential 1-to-2 clock/data distribution chip with internal source termination and CML output structure, optimized for low skew and minimal jitter. The device produces two identical output copies of clock or data operating up to 8 GHz or 12 Gb/s, respectively.Inputs incorporate internal 50 Ohm termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), CML, LVCMOS, LVTTL, or LVDS. Differential 16mA CML (Current Mode Logic) output provides matching 50 Ohm terminations, and 400 mV output swings when externally terminated, 50 Ohm to VCC.

特性 Features

• Maximum Input Clock up to 8 GHz Typical
• Maximum Input Data Rate up to 12Gb/s Typical
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• 30 ps Typical Rise and Fall Times
• 110 ps Typical Propogation Delay
• 3 ps Typical Within Device Skew
• Operatiing Range: VCC = 2.375V to 3.465V with VEE = 0V
• CML Output Level (400 mV Peak-to-Peak Output) Differential Output Only
• 50 Ω Internal Input and Output Termination Resistors
• Functionally Compatible with Existing 2.5V / 3.3V LVEL,LVEP, EP, and SG DEvices
• Pb-Free Packages are Available

应用 Application

• OC-48 & OC-192 SONET/SDH data routing
• Serial Digital HDTV Video Routing
• ATE High Speed Data Communications Links

简介

NB7L11M属于开发板套件编程器的评估演示板及套件。由制造生产的NB7L11M评估和演示板及套件该系列产品提供了一种方便的方法，在经过验证的实施环境中评估某些重点器件的性能或特性。评估方法通常有完善的文档说明，并且视乎具体情况由评估软件提供支持。产品通常由印刷电路板组成，板上已装有重点器件以及必要或有用的支持元器件，另外也可能包括其他组件，例如电缆或电源。对于数量特别多或类别独特的器件类别(如 ADC、DAC 和开关模式电源)，评估平台可组合为一个单独的产品系列。