NB3N121K中文资料Clock / Data Fanout Buffer, 1:21 Differential, 3.3 V, with HCSL Outputs数据手册ONSEMI规格书

描述 Description

The NB3N121K is a differential 1:21 Clock and Data fanout buffer with High-speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N121K is designedwith HCSL PCI Express clock distribution and FBDIMM applications in mind.

特性 Features

• Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and400 MHz
• 340 ps Typical Rise and Fall Times
• 800 ps Typical Propagation Delay
• 100 ps Max Within Device Skew
• 150 ps Max DevicetoDevice Skew
• Delta-tpd 100 ps Maximum Propagation Delay Variation Per Each Differential Pair
• 0.1 ps Typical RMS Additive Phase Jitter
• LVDS Output Levels Optional with Interface Termination
• Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
• Typical HCSL Output Level (700 mV PeaktoPeak)

应用 Application

• Clock Distribution
• PCIe I, II, III
• Networking
• High End Computing
• Routers
• Servers

简介

NB3N121K属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的NB3N121K时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。