Dual J-K negative edge-triggered flip-flop

DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level

文件：83.94 Kbytes 页数：10 Pages

PHI

PHI

Dual J-K negative edge-triggered flip-flop

DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level

文件：83.94 Kbytes 页数：10 Pages

PHI

PHI

Dual J-K negative edge-triggered flip-flops without reset

DESCRIPTION The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level

文件：81.65 Kbytes 页数：10 Pages

PHI

PHI

Dual J-K negative edge-triggered flip-flops without reset

DESCRIPTION The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level

文件：81.65 Kbytes 页数：10 Pages

PHI

PHI

Dual J-K negative edge-triggered flip-flop with common clock and reset

DESCRIPTION The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with common clock and reset inputs, features individual J, K, Clock (CP), Set (SD) and Reset (RD) inputs, true and complementary outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table

文件：51.33 Kbytes 页数：6 Pages

PHI

PHI

Dual J-K negative edge-triggered flip-flop with common clock and reset

DESCRIPTION The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with common clock and reset inputs, features individual J, K, Clock (CP), Set (SD) and Reset (RD) inputs, true and complementary outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table

文件：51.33 Kbytes 页数：6 Pages

PHI

PHI

Triple 3-input NAND gate

74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate

文件：72.11 Kbytes 页数：8 Pages

PHI

PHI

Triple 3-input NAND gate

74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate

文件：72.11 Kbytes 页数：8 Pages

PHI

PHI

Dual J-K negative edge-triggered flip-flops without reset

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Dual J-K negative edge-triggered flip-flop with common clock and reset

恩XP