Process Geometry

Features • Low Noise: 1.5 nV/√Hz Typical • Typical Input Capacitance: 12pF • Typical Breakdown Voltage: -60V • High Input Impedance • Small Die: 518um X 518um X 203um • Bond Pads: 90um X 90um • Substrate Connected to Gate • Au Back-Side Finish Applications • Low Noise Amplifier • Audi

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InterFET

Geometry Types

InterFET

Platinum Thin Film (PTF) Temperature Elements

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TEC

泰科电子

2.5 V, 212.00 MHz LVDS Voltage-Controlled Clock Oscillator (VCXO) PureEdge Product Series

文件：152.18 Kbytes 页数：7 Pages

ONSEMI

安森美半导体

2.5 V, 212.00 MHz LVDS Voltage-Controlled Clock Oscillator (VCXO) PureEdge Product Series

文件：152.18 Kbytes 页数：7 Pages

ONSEMI

安森美半导体