MM54HC107

Dual J-K Flip-Flops with Clear; Typical propagation delay: 16 ns\nWide operating voltage range: 2± 6V\nLow input current: 1mA maximum\nLow quiescent current: 40mA (74HC series)\nHigh output drive: 10 LS-TTL loads;

General Description\nThese J-K Flip-Flops utilize advanced silicon-gate CMOS technology to achieve the high noise immunity and low power dissipation of standard CMOS integrated circuits. These devices can drive 10 LS-TTL loads. These flip-flops are edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, CLOCK, and CLEAR inputs and Q and Q outputs. CLEAR is independent of the clock and accomplished by a low level on the input.\nThe 54HC/74HC logic family is functionally as well as pin out compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCCand ground.

MM54HC107

MM54HC107/MM74HC107 Dual J-K Flip-Flops with Clear

MM54HC107J

MM54HC107/MM74HC107 Dual J-K Flip-Flops with Clear

CD54HC107

DualJ-KFlip-FlopwithResetNegative-EdgeTrigger

Features •HysteresisonClockInputsforImprovedNoiseImmunity andIncreasedInputRiseandFallTimes •AsynchronousReset •ComplementaryOutputs •BufferedInputs •TypicalfMAX=60MHzatVCC=5V,CL=15pF, TA=25oC •Fanout(OverTemperatureRange) -StandardOutputs.....

CD54HC107

DualJ-KFlip-FlopwithResetNegative-EdgeTrigger

CD54HC107

DualJ-KFlip-FlopwithResetNegative-EdgeTrigger

CD54HC107

DualJ-KFlip-FlopwithResetNegative-EdgeTrigger

M54HC107

DUALJ-KFLIPFLOPWITHCLEAR