MM54HC107/MM74HC107 Dual J-K Flip-Flops with Clear

文件：130.979 Kbytes 页数：6 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

Dual J-K Flip-Flops with Clear

General Description\nThese J-K Flip-Flops utilize advanced silicon-gate CMOS technology to achieve the high noise immunity and low power dissipation of standard CMOS integrated circuits. These devices can drive 10 LS-TTL loads. These flip-flops are edge sensitive to the clock input and change state Typical propagation delay: 16 ns\nWide operating voltage range: 2± 6V\nLow input current: 1mA maximum\nLow quiescent current: 40mA (74HC series)\nHigh output drive: 10 LS-TTL loads;

TI

德州仪器

MM54HC107/MM74HC107 Dual J-K Flip-Flops with Clear

文件：130.979 Kbytes 页数：6 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：624.14 Kbytes 页数：16 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：451.69 Kbytes 页数：15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：266.26 Kbytes 页数：11 Pages

TI

德州仪器