MM54HC107中文资料Dual J-K Flip-Flops with Clear数据手册TI规格书

描述 Description

General Description
These J-K Flip-Flops utilize advanced silicon-gate CMOS technology to achieve the high noise immunity and low power dissipation of standard CMOS integrated circuits. These devices can drive 10 LS-TTL loads. These flip-flops are edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, CLOCK, and CLEAR inputs and Q and Q outputs. CLEAR is independent of the clock and accomplished by a low level on the input.
The 54HC/74HC logic family is functionally as well as pin out compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCCand ground.

特性 Features

Typical propagation delay: 16 ns
Wide operating voltage range: 2± 6V
Low input current: 1mA maximum
Low quiescent current: 40mA (74HC series)
High output drive: 10 LS-TTL loads