| 型号 | 下载 订购 | 功能描述 | 制造商 上传企业 | LOGO |
|---|---|---|---|---|
CD54HC107 | Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . 文件:609.54 Kbytes 页数:20 Pages | TI 德州仪器 | TI | |
CD54HC107 | Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件:266.26 Kbytes 页数:11 Pages | TI 德州仪器 | TI | |
CD54HC107 | Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件:451.69 Kbytes 页数:15 Pages | TI 德州仪器 | TI | |
CD54HC107 | Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件:624.14 Kbytes 页数:16 Pages | TI 德州仪器 | TI | |
CD54HC107 | 具有复位功能的高速 CMOS 逻辑双路负边沿触发式 J-K 触发器 The HC107 and HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.\n\n These flip-flops have independent J, K, Reset and Clo • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times\n• Complementary Outputs\n• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C\n• Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads\n• Wide Operating Temperature Range . . . -55°C to 125°; | TI 德州仪器 | TI | |
丝印:5962-8515401CA;Package:CDIP;Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . 文件:609.54 Kbytes 页数:20 Pages | TI 德州仪器 | TI | ||
丝印:5962-8515401CA;Package:CDIP;Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . 文件:609.54 Kbytes 页数:20 Pages | TI 德州仪器 | TI | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件:451.69 Kbytes 页数:15 Pages | TI 德州仪器 | TI | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件:624.14 Kbytes 页数:16 Pages | TI 德州仪器 | TI | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件:624.14 Kbytes 页数:16 Pages | TI 德州仪器 | TI |
技术参数
- Technology Family:
HC
- Supply voltage (Min) (V):
2
- Supply voltage (Max) (V):
6
- Input type:
LVTTL/CMOS
- Output type:
Push-Pull
- Clock Frequency (MHz):
20
- ICC (Max) (uA):
80
- IOL (Max) (mA):
-6
- IOH (Max) (mA):
6
- Features:
Balanced outputs
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI德州仪器 |
22+ |
24000 |
原装正品现货,实单可谈,量大价优 |
询价 | |||
TI |
25+ |
2 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
询价 | |||
TI |
23+ |
DIP陶瓷 |
5000 |
原装正品,假一罚十 |
询价 | ||
TI |
三年内 |
1983 |
只做原装正品 |
询价 | |||
TI |
25+ |
14L CDIP (J) |
8880 |
原装认准芯泽盛世! |
询价 | ||
TI |
0007;0112;0221 |
14L CDIP (J) |
10 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
询价 | ||
Texas Instruments |
2022+ |
原厂原包装 |
8600 |
全新原装 支持表配单 中国著名电子元器件独立分销 |
询价 | ||
TI/德州仪器 |
24+ |
14L CDIP (J) |
1500 |
只供应原装正品 欢迎询价 |
询价 | ||
TI |
23+ |
14L CDIP (J) |
5000 |
全新原装,支持实单,非诚勿扰 |
询价 | ||
TI/德州仪器 |
2023+ |
DIP |
20000 |
AI智能識别、工業、汽車、醫療方案LPC批量及配套一站 |
询价 |
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