丝印：5962-8515401CA；Package：CDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 页数：20 Pages

TI

德州仪器

丝印：5962-8515401CA；Package：CDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 页数：20 Pages

TI

德州仪器

丝印：5962-8515401CA；Package：CDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 页数：20 Pages

TI

德州仪器

丝印：5962-8515401CA；Package：CDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . .

文件：609.54 Kbytes 页数：20 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：451.69 Kbytes 页数：15 Pages

TI

德州仪器

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：624.14 Kbytes 页数：16 Pages

TI

德州仪器