FRAME RATE COMMUNICATIONS PLL

Features • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • For jitter attenuation, use the MK2049

文件：432 Kbytes 页数：12 Pages

RENESAS

瑞萨

丝印：157401ASLF；Package：SOIC；FRAME RATE COMMUNICATIONS PLL

Features • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • For jitter attenuation, use the MK2049

文件：432 Kbytes 页数：12 Pages

RENESAS

瑞萨

丝印：157401ASLF；Package：SOIC；FRAME RATE COMMUNICATIONS PLL

Features • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • For jitter attenuation, use the MK2049

文件：432 Kbytes 页数：12 Pages

RENESAS

瑞萨

丝印：157401ASLF；Package：SOIC；FRAME RATE COMMUNICATIONS PLL

Features • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • For jitter attenuation, use the MK2049

文件：432 Kbytes 页数：12 Pages

RENESAS

瑞萨

丝印：157401ASLF；Package：SOIC；FRAME RATE COMMUNICATIONS PLL

Features • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • For jitter attenuation, use the MK2049

文件：432 Kbytes 页数：12 Pages

RENESAS

瑞萨

丝印：MK1574-01S；Package：SOIC；3.3 VOLT FRAME RATE COMMUNICATIONS PLL

Features • 3.3 volt operation • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • Available in Pb (lead) free package • For jitter attenuation, use the M

文件：385.15 Kbytes 页数：11 Pages

RENESAS

瑞萨

Frame Rate Communications PLL

Description The MK1574-01 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference, and generates many popular communications frequencies. All outputs are frequency locked together and to the input. This allows for the generation of locked clocks to

文件：83.69 Kbytes 页数：6 Pages

ICST

Frame Rate Communications PLL

Description The MK1574-01 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference, and generates many popular communications frequencies. All outputs are frequency locked together and to the input. This allows for the generation of locked clocks to

文件：83.69 Kbytes 页数：6 Pages

ICST

丝印：MK1574-01SI；Package：SOIC；3.3 VOLT FRAME RATE COMMUNICATIONS PLL

Features • 3.3 volt operation • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • Available in Pb (lead) free package • For jitter attenuation, use the M

文件：385.15 Kbytes 页数：11 Pages

RENESAS

瑞萨

丝印：MK1574-01SILF；Package：SOIC；3.3 VOLT FRAME RATE COMMUNICATIONS PLL

Features • 3.3 volt operation • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • Available in Pb (lead) free package • For jitter attenuation, use the M

文件：385.15 Kbytes 页数：11 Pages

RENESAS

瑞萨