TRIPLE 3-INPUT AND GATE

Triple 3-Input AND Gate High−Performance Silicon−Gate CMOS Features • Outputs Source/Sink 24 mA • ′ACT11 Has TTL Compatible Inputs • These are Pb−Free Devices

文件：126.8 Kbytes 页数：5 Pages

ONSEMI

安森美半导体

Triple 3?묲nput AND Gate

Features • Outputs Source/Sink 24 mA • ′ACT11 Has TTL Compatible Inputs • Pb−Free Packages are Available

文件：131.07 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Triple 3-Input AND Gate

文件：72.31 Kbytes 页数：6 Pages

ONSEMI

安森美半导体

Triple 3?묲nput AND Gate

文件：131.07 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

TRIPLE 3-INPUT AND GATE

Triple 3-Input AND Gate• Outputs Source/Sink 24 mA\n• ′ACT11 Has TTL Compatible Inputs

恩XP

恩智浦

Triple 3-Input AND Gate

• Outputs Source/Sink 24 mA\n• ACT11 Has TTL Compatible Inputs\n• Pb-Free Packages Are Available;

ONSEMI

安森美半导体

Dual JK Negative Edge-Triggered Flip-Flop

Dual JK Negative Edge-Triggered Flip-Flop The MC74AC113/74ACT113 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC

文件：188.34 Kbytes 页数：6 Pages

Motorola

摩托罗拉

Triple 3?묲nput AND Gate

Features • Outputs Source/Sink 24 mA • ′ACT11 Has TTL Compatible Inputs • Pb−Free Packages are Available

文件：131.07 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Triple 3?묲nput AND Gate

Features • Outputs Source/Sink 24 mA • ′ACT11 Has TTL Compatible Inputs • Pb−Free Packages are Available

文件：131.07 Kbytes 页数：9 Pages

ONSEMI

安森美半导体

Triple 3?묲nput AND Gate

Features • Outputs Source/Sink 24 mA • ′ACT11 Has TTL Compatible Inputs • Pb−Free Packages are Available

文件：131.07 Kbytes 页数：9 Pages

ONSEMI

安森美半导体