MC14LC5540 ADPCM Codec Evaluation Kit

Advance Information MC14LC5540 ADPCM Codec Evaluation Kit The MC145537EVK is the evaluation platform for the MC14LC5540 ADPCM Codec. This board provides the clock generator circuitry and microcontroller interface to facilitate the evaluation of the MC14LC5540. MC145537EVK Hardware F

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3-Digit BCD Counter

3-Digit BCD Counter  The MC14553B 3–digit BCD counter consists of 3 negative edgetriggered BCDcounters that are cascadedsynchronously. A quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providingone BCD nu

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3-Digit BCD Counter

3-Digit BCD Counter The MC14553B 3−digit BCD counter consists of 3 negative edge triggered BCD counters that are cascaded synchronously. A quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providing one BCD number or di

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3-Digit BCD Counter

3-Digit BCD Counter The MC14553B 3−digit BCD counter consists of 3 negative edge triggered BCD counters that are cascaded synchronously. A quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providing one BCD number or di

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3-Digit BCD Counter

3-Digit BCD Counter The MC14553B 3−digit BCD counter consists of 3 negative edge triggered BCD counters that are cascaded synchronously. A quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providing one BCD number or di

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2-Bit by 2-Bit Parallel Binary Multiplier

The MC14554B 2 x 2–bit parallel binary multiplier is constructed with complementary MOS (CMOS) enhancement mode devices. The multiplier can perform the multiplication of two binary numbers and simultaneously add two other binary numbers to the product. The MC14554B has two multiplicand inputs (X0

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ADPCM Codec

INTRODUCTION The MC145540 ADPCM Codec is a single chip implementation of a PCM codec-filter and an ADPCM encoder/decoder, and therefore provides an efficient solution for applications requiring the digitization and compression of voiceband signals. This device is designed to operate over a wide v

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2-Bit by 2-Bit Parallel Binary Multiplier

The MC14554B 2 x 2–bit parallel binary multiplier is constructed with complementary MOS (CMOS) enhancement mode devices. The multiplier can perform the multiplication of two binary numbers and simultaneously add two other binary numbers to the product. The MC14554B has two multiplicand inputs (X0

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PCM Codec-Filter

PCM Codec-Filter TheMC145554, MC145557, MC145564, and MC145567 are all per channel PCM Codec–Filters. These devices perform the voice digitization and reconstruction as well as the band limiting and smoothing required for PCM systems.They are designed to operate in both synchronous and asynch

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Dual Binary to 1-of-4 Decoder/Demultiplexer

Dual Binary to 1−of−4 Decoder/Demultiplexer The MC14555B and MC14556B are constructed with complementary MOS (CMOS) enhancement mode devices. Each Decoder/Demultiplexer has two select inputs (A and B), an active low Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2, Q3). The M

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