3-BIT 4:1 MUX-LATCH

The MC10E/100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs (see logic symbol). When the Latch Enable (LEN) is LOW, the latch is transparent, and output data is controlled by the m

文件：110.02 Kbytes 页数：5 Pages

ONSEMI

安森美半导体

3-BIT 4:1 MUX-LATCH

文件：63 Kbytes 页数：4 Pages

Micrel

麦瑞半导体

3-BIT 4:1 MUX-LATCH

DESCRIPTION The SY10/100E256 offer three 4:1 multiplexers followed by latches with differential outputs designed for use in new, high-performance ECL systems. Separate Select controls are provided for the leading 2:1 mux pairs (see block diagram). FEATURES ■ 950ps max. data to output ■ Extende

文件：60.86 Kbytes 页数：4 Pages

Micrel

麦瑞半导体

3-BIT 4:1 MUX-LATCH

DESCRIPTION The SY10/100E256 offer three 4:1 multiplexers followed by latches with differential outputs designed for use in new, high-performance ECL systems. Separate Select controls are provided for the leading 2:1 mux pairs (see block diagram). FEATURES ■ 950ps max. data to output ■ Extende

文件：60.86 Kbytes 页数：4 Pages

Micrel

麦瑞半导体