5-BIT 2:1 MUX-LATCH

Description The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2

文件：107.22 Kbytes 页数：4 Pages

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5V ECL 5-Bit 2:1 Mux-Latch

文件：127.21 Kbytes 页数：8 Pages

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MC10E154: ECL 5-Bit 2:1 Mux Latch

The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2 (or both) latc 850ps Max. LEN to Output\n825ps Max. D to Output\nDifferential Outputs\nAsynchronous Master Reset\nDual Latch-Enables\nPECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V\nNECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V\nInternal Input Pulldown Resistors\nESD Protection: ;

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5-BIT 2:1 MUX-LATCH

Description The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2

文件：107.22 Kbytes 页数：4 Pages

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安森美半导体

5V ECL 5-Bit 2:1 Mux-Latch

文件：127.21 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL 5-Bit 2:1 Mux-Latch

文件：127.21 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL 5-Bit 2:1 Mux-Latch

文件：127.21 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL 5-Bit 2:1 Mux-Latch

文件：127.21 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL 5-Bit 2:1 Mux-Latch

文件：127.21 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

Package：28-LCC（J 形引线）；包装：管件 类别：集成电路（IC） 信号开关，多路复用器，解码器 描述：IC MULTIPLEXER 5 X 2:1 28PLCC

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