MC100LVEP34中文资料2.5 V / 3.3 V ECL ÷2, ÷4, ÷8 Clock Generation Chip数据手册ONSEMI规格书

描述 Description

The MC100LVEP34 is a low skew DIV2, DIV4, DIV8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers aresynchronous to each other, therefore, the common output edges are all preciselyaligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The common enable (ENbar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input.Upon startup, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple LVEP34s in a system.Single-ended CLK input operation is limited to a VCC of ≥ 3.0 V in PECL mode, or VEE ≤ -3.0 V in NECL mode.

特性 Features

• 35 ps Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• The 100 Series Contains Temperature Compensation.
• PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V
• Open Input Default State
• LVDS Input Compatible

简介

MC100LVEP34属于集成电路（IC）的时钟发生器PLL频率合成器。由制造生产的MC100LVEP34时钟发生器，PLL，频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲，这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。