MC100LVEL51数据手册集成电路（IC）的触发器规格书PDF

描述 Description

The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from a 3.3V supply. With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applications which require the ultimate in AC performance at 3.3V VCC. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the LVEL51 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLKbar input will be biased at VCC/2.

特性 Features

• 475ps Propagation Delay
• 2.8GHz Toggle Frequency
• ESD Protection: >4 KV HBM, >200 V MM
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V
• NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -3.8 V
• Internal Input Pulldown Resistors
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL-94 code V-0 @ 1/8\", Oxygen Index 28 to 34
• Transistor Count = 114 devices
• Pb-Free Packages are Available

应用 Application

• 2.8GHz Toggle Frequency

简介

MC100LVEL51属于集成电路（IC）的触发器。由制造生产的MC100LVEL51触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。