MC100LVE310数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The MC100LVE310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The LVE310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees. To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50, even if only one side is being used. In most applications all eight differential pairs will be used and therefore terminated. In the case where fewer than eight pairs are used it is necessary to terminate at least the output pairs adjacent to the output pair being used in order to maintain minimum skew. Failure to follow this guideline will result in small degradations of propagation delay (on the order of 10-20 ps) of the outputs being used, while not catastrophic to most designs this will result in an increase in skew. Note that the package corners isolate outputs from one another such that the guideline expressed above holds only for outputs on the same side of the package. The MC100LVE310, as with most ECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVE310 to be used for high performance clock distribution in +3.3 V systems. Designers can take advantage of the LVE310's performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage of VCC-2.0 V will need to be provided. For more information on using PECL, designers should refer to Application Note AN1406/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connecte

特性 Features

• 200ps Part-to-Part Skew
• 50ps Output-to-Output Skew
• The 100 Series Contains Temperature Compensation
• ESD Protection: >2 KV HBM, >200 V MM
• PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V
• Internal Input Pulldown Resistors
• Q Output will Default LOW with All Inputs Open or at VEE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL-94 code V-0 @ 1/8\", Oxygen Index 28 to 34
• Transistor Count = 212 devices
• Pb-Free Packages are Available

简介

MC100LVE310属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的MC100LVE310时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。