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MC100LVEL34数据手册集成电路(IC)的时钟发生器PLL频率合成器规格书PDF

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厂商型号

MC100LVEL34

参数属性

MC100LVEL34 封装/外壳为16-SOIC(0.154",3.90mm 宽);包装为管件;类别为集成电路(IC)的时钟发生器PLL频率合成器;产品描述:IC CLOCK GEN 2/4/8 3.3V 16-SOIC

功能描述

3.3 V ECL ÷·2,÷·4,÷·8 分频器
IC CLOCK GEN 2/4/8 3.3V 16-SOIC

封装外壳

16-SOIC(0.154",3.90mm 宽)

制造商

ONSEMI ON Semiconductor

中文名称

安森美半导体 安森美半导体公司

数据手册

原厂下载下载地址下载地址二

更新时间

2025-8-15 23:01:00

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MC100LVEL34规格书详情

描述 Description

The MC100LVEL34 is a low skew 2, 4, 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The common enable (EN bar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulsecould lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input.Upon start−up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internaldividers, as well as multiple LVEL34s in a system.

特性 Features

• 50 ps Typical Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• 1.5 GHz Toggle Frequency
• The 100 Series Contains Temperature Compensation.
• PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0V
• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V
• Open Input Default State
• LVDS Input Compatible
• Pb-Free Packages are Available

简介

MC100LVEL34属于集成电路(IC)的时钟发生器PLL频率合成器。由制造生产的MC100LVEL34时钟发生器,PLL,频率合成器时钟发生器、PLL 和频率合成器集成电路 (IC) 可为逻辑器件提供参考信号的稳定定时脉冲,这些器件包括计算机、微控制器、数据通信系统和图形/视频发生器。这些集成电路可能包括缓冲器、驱动器、分频器、倍频器、多路复用器、合成器、扇出分配器和预分频器。

技术参数

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  • 产品编号:

    MC100LVEL34DR2

  • 制造商:

    onsemi

  • 类别:

    集成电路(IC) > 时钟发生器,PLL,频率合成器

  • 系列:

    100LVEL

  • 包装:

    管件

  • 类型:

    时钟发生器

  • PLL:

  • 输入:

    LVDS,NECL,PECL

  • 输出:

    ECL

  • 比率 - 输入:

    1:4

  • 差分 - 输入:

    是/是

  • 频率 - 最大值:

    1.5GHz

  • 分频器/倍频器:

    是/无

  • 电压 - 供电:

    3V ~ 3.8V

  • 工作温度:

    -40°C ~ 85°C

  • 安装类型:

    表面贴装型

  • 封装/外壳:

    16-SOIC(0.154",3.90mm 宽)

  • 供应商器件封装:

    16-SOIC

  • 描述:

    IC CLOCK GEN 2/4/8 3.3V 16-SOIC

供应商 型号 品牌 批号 封装 库存 备注 价格
ON(安森美)
24+
NA/
8735
原厂直销,现货供应,账期支持!
询价
onsemi(安森美)
24+
TSSOP16
7350
现货供应,当天可交货!免费送样,原厂技术支持!!!
询价
onsemi
25+
原厂封装
10280
原厂授权代理,专注军工、汽车、医疗、工业、新能源!
询价
ON
23+
SOP-16
7566
原厂原装
询价
ON
25+
SOIC16
3000
全新原装、诚信经营、公司现货销售!
询价
ON
2018+
SOIC16
6528
科恒伟业!承若只做进口原装正品假一赔十!1581728776
询价
ON/安森美
22+
N/A
12245
现货,原厂原装假一罚十!
询价
ON/安森美
23+
NA
25630
原装正品
询价
ON
24+
TSSOP-16
25000
ON全系列可订货
询价
ON
24+/25+
114
原装正品现货库存价优
询价