3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator

Description The MC100LVELT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which require th

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3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator

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3.3V Dual Differential LVPECL/LVDS to LVTTL Translator

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转换器，双差分 LVPECL 到 LVTTL

The MC100LVELT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL (Positive ECL) levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the LVELT23 makes it ideal for applications which require the translation of a clock • 2.0ns Typical Propagation Delay\n• Maximum Frequency > 180 MHz\n• Differential LVPECL Inputs\n• PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with GND= 0 V\n• 24 mA LVTTL Outputs\n• Flow Through Pinouts\n• Internal Pulldown Resistors\n• Q Output will default LOW with inputs open or at GND\n• ESD ;

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3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator

Description The MC100LVELT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which require th

文件：66.96 Kbytes 页数：8 Pages

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安森美半导体

3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator

Description The MC100LVELT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which require th

文件：66.96 Kbytes 页数：8 Pages

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安森美半导体

3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator

Description The MC100LVELT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which require th

文件：66.96 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator

Description The MC100LVELT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which require th

文件：66.96 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator

Description The MC100LVELT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which require th

文件：66.96 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator

Description The MC100LVELT23 is a dual differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead package and the dual gate design of the LVELT23 makes it ideal for applications which require th

文件：66.96 Kbytes 页数：8 Pages

ONSEMI

安森美半导体