Low Voltage 2.5V/3.3V Differential ECL/ PECL/HSTL Fanout Buffer

Features • Dual 1:5 differential clock distribution • 30 ps maximum device skew • Fully differential architecture from input to all outputs • SiGe technology supports near-zero output skew • Supports DC to 3GHz operation of clock or data signals • ECL/PECL compatible differential clock outpu

文件：546.4 Kbytes 页数：11 Pages

RENESAS

瑞萨

Low Voltage 2.5/3.3 V Differential ECL/PECL/HSTL Fanout Buffer

文件：226.04 Kbytes 页数：8 Pages

freescaleFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

Low Voltage 2.5V/3.3V Differential ECL/PECL/HSTL Fanout Buffer

The MC100ES6210 is designed for low skew clock distribution systems and supports clock frequencies up to 3GHz. The device consists of two independent 1:5 clock fanout buffers. The input signal of each fanout buffer is distributed to five identical, differential ECL/ PECL outputs. Both CLKA and CLKB Dual 1:5 differential clock distribution\n30 ps maximum device skew\nFully differential architecture from input to all outputs\nSiGe technology supports near-zero output skew\nSupports DC to 3GHz operation of clock or data signals\nECL/PECL compatible differential clock outputs\nECL/PECL compatible ;

Renesas

瑞萨

Low Voltage 2.5V/3.3V Differential ECL/ PECL/HSTL Fanout Buffer

Features • Dual 1:5 differential clock distribution • 30 ps maximum device skew • Fully differential architecture from input to all outputs • SiGe technology supports near-zero output skew • Supports DC to 3GHz operation of clock or data signals • ECL/PECL compatible differential clock outpu

文件：546.4 Kbytes 页数：11 Pages

RENESAS

瑞萨

Low Voltage 2.5V/3.3V Differential ECL/ PECL/HSTL Fanout Buffer

Features • Dual 1:5 differential clock distribution • 30 ps maximum device skew • Fully differential architecture from input to all outputs • SiGe technology supports near-zero output skew • Supports DC to 3GHz operation of clock or data signals • ECL/PECL compatible differential clock outpu

文件：546.4 Kbytes 页数：11 Pages

RENESAS

瑞萨

Low Voltage 2.5V/3.3V Differential ECL/ PECL/HSTL Fanout Buffer

Features • Dual 1:5 differential clock distribution • 30 ps maximum device skew • Fully differential architecture from input to all outputs • SiGe technology supports near-zero output skew • Supports DC to 3GHz operation of clock or data signals • ECL/PECL compatible differential clock outpu

文件：546.4 Kbytes 页数：11 Pages

RENESAS

瑞萨

Low Voltage 2.5/3.3 V Differential ECL/PECL/HSTL Fanout Buffer

文件：226.04 Kbytes 页数：8 Pages

freescaleFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

Low Voltage 2.5/3.3 V Differential ECL/PECL/HSTL Fanout Buffer

文件：226.04 Kbytes 页数：8 Pages

freescaleFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

IC CLK BUFFER 1:5 3GHZ 32TQFP

Renesas

瑞萨

IC CLK BUFFER 1:5 3GHZ 32VFQFPN

Renesas

瑞萨