6-BIT D REGISTER

Description The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 (or both) go HIGH. The asynchronous Master Reset (MR) makes all Q outputs g

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5V ECL 6-Bit D Register

文件：127.84 Kbytes 页数：8 Pages

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MC100E151: ECL 6-Bit D Flip-Flop Register

The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 (or both) go HIGH. The asynchronous Master Reset (MR) makes all Q outputs go LOW.The 100 S 1100MHz Min. Toggle Frequency\nDifferential Outputs\nAsynchronous Master Reset\nDualClocks\nPECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V\nNECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V\nInternal Input Pulldown Resistors\nESD Protection: > 2 kV HBM, > 200 V MM\nMee;

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5V ECL 6-Bit D Register

文件：127.84 Kbytes 页数：8 Pages

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5V ECL 6-Bit D Register

文件：127.84 Kbytes 页数：8 Pages

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5V ECL 6?륛it D Register

文件：155.48 Kbytes 页数：7 Pages

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5V ECL 6-Bit D Register

文件：127.84 Kbytes 页数：8 Pages

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5V ECL 6-Bit D Register

文件：127.84 Kbytes 页数：8 Pages

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包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 计数器，除法器 描述：IC FF D-TYPE SNGL 6BIT 28PLCC

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Package：28-LCC（J 形引线）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 6BIT 28PLCC

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