3-BIT 4:1 MUX-LATCH

The MC10E/100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs (see logic symbol). When the Latch Enable (LEN) is LOW, the latch is transparent, and output data is controlled by the m

文件：110.02 Kbytes 页数：5 Pages

ONSEMI

安森美半导体

5V ECL Low Voltage 2:8 Differential Fanout Buffer

Description The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test

文件：133.68 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL Low Voltage 2:8 Differential Fanout Buffer

Description The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test

文件：133.68 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL Low Voltage 2:8 Differential Fanout Buffer

Description The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test

文件：133.68 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL Low Voltage 2:8 Differential Fanout Buffer

Description The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test

文件：133.68 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

5V ECL Low Voltage 2:8 Differential Fanout Buffer

Description The MC100E310 is a low voltage, low skew 2:8 differential ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test

文件：133.68 Kbytes 页数：8 Pages

ONSEMI

安森美半导体

3-BIT REGISTERED BUS TRANSCEIVER

The MC10E/MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs (BUS0–BUS2) are specified for driving a 25 Ω bus; the receive outputs (Q0 – Q2) are specified for 50 Ω. The bus outputs feature a normal HIGH level (VOH) and a cutoff LOW level — when LOW,

文件：113.66 Kbytes 页数：4 Pages

ONSEMI

安森美半导体

3-BIT SCANNABLE REGISTERED BUS TRANSCEIVER

The MC10E/100E337 is a 3-bit registered bus transceiver with scan. The bus outputs (BUS0–BUS2) are specified for driving a 25 Ω bus; the receive outputs (Q0 – Q2) are specified for 50 Ω. The bus outputs feature a normal HIGH level (VOH) and a cutoff LOW level — when LOW, the outputs go to – 2.0 V

文件：116.81 Kbytes 页数：5 Pages

ONSEMI

安森美半导体

QUAD DIFFERENTIAL AND/NAND

The MC10E404/100E404 is a 4-bit differential AND/NAND device. The differential operation of the device makes it ideal for pulse shaping applications where duty cycle skew is critical. Special design techniques were incorporated to minimize the skew between the upper and lower level gate inputs. T

文件：108.26 Kbytes 页数：4 Pages

ONSEMI

安森美半导体

QUAD DIFFERENTIAL AND/NAND

The MC10E404/100E404 is a 4-bit differential AND/NAND device. The differential operation of the device makes it ideal for pulse shaping applications where duty cycle skew is critical. Special design techniques were incorporated to minimize the skew between the upper and lower level gate inputs. T

文件：108.26 Kbytes 页数：4 Pages

ONSEMI

安森美半导体