8-BIT SYNCHRONOUS BINARY UP COUNTER

Description The MC10E/100E016 is a high−speed synchronous, presettable, cascadable 8−bit binary counter. Architecture and operation are the same as the MC10H016 in the MECL 10H™ family, extended to 8−bits, as shown in the logic symbol. Features • 700 MHz Min. Count Frequency • 1000 ps CLK

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5V ECL Quad 4짯Input OR/NOR Gate

Description The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. Features • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7

文件：69.51 Kbytes 页数：8 Pages

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QUAD 4-INPUT OR/NOR GATE

The MC10E/100E101 is a quad 4-input OR/NOR gate. • 500ps Max. Propagation Delay • Extended 100E VEE Range of – 4.2V to – 5.46V • 75kΩ Input Pulldown Resistors

文件：98.62 Kbytes 页数：4 Pages

MOTOROLA

摩托罗拉

5V ECL Quad 4짯Input OR/NOR Gate

Description The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. Features • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7

文件：69.51 Kbytes 页数：8 Pages

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5V ECL Quad 4짯Input OR/NOR Gate

Description The MC10E/100E101 is a quad 4-input OR/NOR gate. The 100 Series contains temperature compensation. Features • 500 ps Max. Propagation Delay • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7

文件：69.51 Kbytes 页数：8 Pages

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QUINT 2-INPUT AND/NAND GATE

Description The MC10E/100E104 is a quint 2-input AND/NAND gate. The function output F is the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be used. The 100 Series contains temperature compensation. Features • 600 ps Max. P

文件：102.63 Kbytes 页数：4 Pages

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QUINT 2-INPUT XOR/XNOR GATE

Description The MC10E/100E107 is a quint 2-input XOR/XNOR gate. The function output F is the OR of all five XOR outputs, while F is the NOR. The Q outputs need not be terminated if only the F outputs are to be used. The 100 Series contains temperature compensation. Features • 600 ps Maximum Pr

文件：102.71 Kbytes 页数：4 Pages

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1:9 DIFFERENTIAL CLOCK DRIVER

Description The MC10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or else single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable i

文件：104.69 Kbytes 页数：5 Pages

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QUAD DRIVER

Description The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock driver, although the M

文件：99.66 Kbytes 页数：4 Pages

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QUINT DIFFERENTIAL LINE RECEIVER

Description The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. For applications which require bandwidths greater than that of the E116, the E416 device may be of interest. Active current sources plus a deep collector feature of the MOSAIC III process provide t

文件：108 Kbytes 页数：4 Pages

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