MC100E336中文资料安森美半导体数据手册PDF规格书

The MC10E/MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs (BUS0–BUS2) are specified for driving a 25 Ω bus; the receive outputs (Q0 – Q2) are specified for 50 Ω. The bus outputs feature a normal HIGH level (VOH) and a cutoff LOW level — when LOW, the outputs go to –2.0 V and the output emitter-follower is “off”, presenting a high impedance to the bus. The bus outputs also feature edge slow-down capacitors.

The 100 Series contains temperature compensation.

• 25 Ω Cutoff Bus Outputs

• 50 Ω Receiver Outputs

• Transmit and Receive Registers

• 1500 ps Max. Clock to Bus

• 1000 ps Max. Clock to Q

• Bus Outputs Feature Internal Edge Slow-Down Capacitors

• Additional Package Ground Pins

• PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V

• NECL Mode Operating Range: VCC= 0 V with VEE= –4.2 V to –5.7 V

• Internal Input Pulldown Resistors

• ESD Protection: > 1 KV HBM, > 75 V MM

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

• Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D

• Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34

• Transistor Count = 430 devices