MBM29LV800BA-90中文资料CMOS 8M (1M × 8/512K × 16) BIT数据手册Fujitsu规格书

描述 Description

■ GENERAL DESCRIPTION
The MBM29LV800TA/BA are a 8M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K words of 16 bits each. The MBM29LV800TA/BA are offered in a 48-pin TSOP(I), 44-pin SOP, and 48-ball FBGA packages. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.■ FEATURES
• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
   44-pin SOP (Package suffix: PF)
   48-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   One 8K word, two 4K words, one 16K word, and fifteen 32K words sectors in word mode
   One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes sectors in byte mode
   Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• Embedded EraseTM Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
   Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
   Suspends the erase operation to allow a read in another sector within the same device
• Sector protection
   Hardware method disables any combination of sectors from program or erase operations
• Sector Protection set function by Extended sector Protect command
• Temporary sector unprotection
   Temporary sector unprotection via the RESET pin

特性 Features

• Single 3.0 V read, program, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
   48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
   44-pin SOP (Package suffix: PF)
   48-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   One 8K word, two 4K words, one 16K word, and fifteen 32K words sectors in word mode
   One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes sectors in byte mode
   Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
   T = Top sector
   B = Bottom sector
• Embedded EraseTM Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
   Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switch themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
   Suspends the erase operation to allow a read in another sector within the same device
• Sector protection
   Hardware method disables any combination of sectors from program or erase operations
• Sector Protection set function by Extended sector Protect command
• Temporary sector unprotection
   Temporary sector unprotection via the RESET pin