Ultra Low-Power, Single/Dual-Supply Comparators

General Description The MAX921–MAX924 single, dual, and quad micropower, low-voltage comparators feature the lowest power consumption available. These comparators draw less than 4µA supply current over temperature (MAX921/MAX922), and include an internal 1.182V ±1 voltage reference, programmable

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Ultra Low-Power, Single/Dual-Supply Comparators

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超低功耗、单/双电源比较器

MAX921–MAX924单、双和四路微功耗、低电压比较器具有超低功耗。在整个工作温度范围内，这些比较器仅消耗不足4µA电源电流(MAX921/MAX922)，并含有一个内置的1.182V ±1%的基准电压源，具有可编程滞回，兼容于TTL/CMOS的输出能够吸收和源出电流。\n\n 此组比较器最适合用于3V或5V单电源系统中，也能够工作于+2.5V至+11V单电源(或±1.25V至±5V双电源)，每路比较器的输入电压摆幅从负电源到低于正电源电压1.3V。\n\n MAX921–MAX924的独特输出级设计可以持续提供高达40mA的电流。由于消除了比较器改变逻辑状态时 • µMAX®及8引脚SO封装(MAX921/MAX922/MAX923)\n• 超低静态电流，全温度范围内最大4µA (MAX921)\n• 供电电源：\n• +2.5V至+11V单电源\n• ±1.25V至±5.5V双电源\n\n\n• 输入电压范围包含了负电源电压\n• 内置1.182V ±1%带隙基准源\n• 可调滞回\n• TTL/CMOS兼容的输出\n• 传输延迟时间12µs (10mV过驱动)\n• 无切换短路电流\n• 可持续提供40mA电流;

ADI

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Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

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Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

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Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

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Programmable DC-Balanced 21-Bit Serializers

General Description The MAX9209/MAX9213 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization. The MAX9209/MAX9213 feature programmable DC balance, which allows isolation between the serializ

文件：477.18 Kbytes 页数：20 Pages

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Programmable DC-Balanced 21-Bit Serializers

General Description The MAX9209/MAX9213 serialize 21 bits of LVTTL/LVCMOS parallel input data to three LVDS outputs. A parallel rate clock on a fourth LVDS output provides timing for deserialization. The MAX9209/MAX9213 feature programmable DC balance, which allows isolation between the serializ

文件：477.18 Kbytes 页数：20 Pages

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Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

文件：904.71 Kbytes 页数：18 Pages

Maxim

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Programmable DC-Balance 21-Bit Deserializers

General Description The MAX9210/MAX9212/MAX9214/MAX9216/MAX9220/MAX9222 deserialize three LVDS serial data inputs into 21 single-ended LVCMOS/LVTTL outputs. A parallel rate LVDS clock received with the LVDS data streams provides timing for deserialization. The outputs have a sepa rate supply, all

文件：904.71 Kbytes 页数：18 Pages

Maxim

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