1Mbit 128K x8, 3.0V Asynchronous SRAM

SUMMARY DESCRIPTION The M68AW127B is a 1Mbit (1,048,576 bit) CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal ad dress access and cycle times. It requires a single 2.7 to 3.6V supply. F

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STMICROELECTRONICS

意法半导体

CHIPS
BGA

CHIPS

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SOURCE
BGA

SOURCE

索尔思光电

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