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M38510/32403BSA

丝印:32403BSA;Package:CFP;SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features 1• Inputs Tolerant Down to 2 V, Compatible With 3.3-V or 2.5-V Logic Inputs • Maximum tpd of 15 ns at 5 V • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • PNP Inputs Reduce DC Loading • Hysteresis at Inputs Improves Noise Margins 2 Applications • Servers

文件:1.80265 Mbytes 页数:41 Pages

TI

德州仪器

M38510/32403SRA

丝印:32403SRA;Package:CDIP;SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features 1• Inputs Tolerant Down to 2 V, Compatible With 3.3-V or 2.5-V Logic Inputs • Maximum tpd of 15 ns at 5 V • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • PNP Inputs Reduce DC Loading • Hysteresis at Inputs Improves Noise Margins 2 Applications • Servers

文件:1.80265 Mbytes 页数:41 Pages

TI

德州仪器

M38510/32403SRA

丝印:JM38510/32403SRA;Package:CDIP;SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features 1• Inputs Tolerant Down to 2 V, Compatible With 3.3-V or 2.5-V Logic Inputs • Maximum tpd of 15 ns at 5 V • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • PNP Inputs Reduce DC Loading • Hysteresis at Inputs Improves Noise Margins 2 Applications • Servers

文件:1.80212 Mbytes 页数:41 Pages

TI

德州仪器

M38510/32403SSA

丝印:JM38510/32403SSA;Package:CFP;SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features 1• Inputs Tolerant Down to 2 V, Compatible With 3.3-V or 2.5-V Logic Inputs • Maximum tpd of 15 ns at 5 V • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • PNP Inputs Reduce DC Loading • Hysteresis at Inputs Improves Noise Margins 2 Applications • Servers

文件:1.80212 Mbytes 页数:41 Pages

TI

德州仪器

M38510/32403SSA

丝印:32403SSA;Package:CFP;SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features 1• Inputs Tolerant Down to 2 V, Compatible With 3.3-V or 2.5-V Logic Inputs • Maximum tpd of 15 ns at 5 V • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • PNP Inputs Reduce DC Loading • Hysteresis at Inputs Improves Noise Margins 2 Applications • Servers

文件:1.80265 Mbytes 页数:41 Pages

TI

德州仪器

M38510/32502B2A

丝印:32502B2A;Package:LCCC;OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件:1.58154 Mbytes 页数:32 Pages

TI

德州仪器

M38510/32502BRA

丝印:32502BRA;Package:CDIP;OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件:1.58154 Mbytes 页数:32 Pages

TI

德州仪器

M38510/32502BSA

丝印:32502BSA;Package:CFP;OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件:1.58154 Mbytes 页数:32 Pages

TI

德州仪器

M38510/32502SRA

丝印:32502SRA;Package:CDIP;OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件:1.58154 Mbytes 页数:32 Pages

TI

德州仪器

M38510/32502SSA

丝印:32502SSA;Package:CFP;OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

文件:1.58154 Mbytes 页数:32 Pages

TI

德州仪器

技术参数

  • 电路数:

    1

  • 压摆率:

    7 V/µs(最小)

  • 增益带宽积:

    3MHz

  • 电流 - 输入偏置:

    50pA

  • 电压 - 输入失调:

    5mV

  • 电流 - 电源:

    4mA

  • 工作温度:

    -55°C ~ 125°C

  • 安装类型:

    通孔

  • 封装/外壳:

    8-CDIP(0.300\,7.62mm)

  • 供应商器件封装:

    8-CDIP

供应商型号品牌批号封装库存备注价格
24+
3000
公司存货
询价
NS
三年内
1983
只做原装正品
询价
MIT
23+
DIP
89630
当天发货全新原装现货
询价
MITSUBISH
100
原装现货,价格优惠
询价
MSC
25+
SOP8
18000
原厂直接发货进口原装
询价
NS
17+
DIP14
6200
100%原装正品现货
询价
PMI
2016+
TO46-8
8880
只做原装,假一罚十,公司可开17%增值税发票!
询价
PHI
CDIP24
93+
13
全新原装进口自己库存优势
询价
SG
24+
SOP
5632
公司原厂原装现货假一罚十!特价出售!强势库存!
询价
NSC
24+
CAN10
5000
原装现货假一罚十
询价
更多M38510供应商 更新时间2025-12-18 16:01:00