12 x 12-bit Parallel Multiplier

DESCRIPTION The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with Fairchilds’s MPY112K. FEATURES ❑ 25 ns Worst-Case Multiply Time ❑ Low Power CMOS Technology ❑ Replaces Fairchild MPY112K ❑ Two

文件：46.51 Kbytes 页数：6 Pages

LODEV

12 x 12-bit Parallel Multiplier

DESCRIPTION The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with Fairchilds’s MPY112K. FEATURES ❑ 25 ns Worst-Case Multiply Time ❑ Low Power CMOS Technology ❑ Replaces Fairchild MPY112K ❑ Two

文件：46.51 Kbytes 页数：6 Pages

LODEV

40 MHz Dual Clock Buffer

文件：975.5 Kbytes 页数：14 Pages

NSC

国半

40 MHz Dual Clock Buffer

文件：1.28796 Mbytes 页数：19 Pages

TI

德州仪器

Small Signal Bandwidth 40 MHz, Supply Voltage Range 2.4V to 5V

文件：1.29642 Mbytes 页数：22 Pages

TI

德州仪器