LMK1D210xL Ultra Low Additive Jitter LVDS Buffer

1 Features • High-performance LVDS clock buffer family: up to 2GHz – Dual 1:2 differential buffer – Dual 1:4 differential buffer – Dual 1:6 differential buffer – Dual 1:8 differential buffer • Supply voltage: 1.71V to 3.465V • Dual output common mode voltage operation: – Output common mod

文件：2.47737 Mbytes 页数：46 Pages

TI

德州仪器

LMK1D210xL Ultra Low Additive Jitter LVDS Buffer

1 Features • High-performance LVDS clock buffer family: up to 2GHz – Dual 1:2 differential buffer – Dual 1:4 differential buffer – Dual 1:6 differential buffer – Dual 1:8 differential buffer • Supply voltage: 1.71V to 3.465V • Dual output common mode voltage operation: – Output common mod

文件：2.47174 Mbytes 页数：46 Pages

TI

德州仪器

LMK1D210xL Ultra Low Additive Jitter LVDS Buffer

1 Features • High-performance LVDS clock buffer family: up to 2GHz – Dual 1:2 differential buffer – Dual 1:4 differential buffer – Dual 1:6 differential buffer – Dual 1:8 differential buffer • Supply voltage: 1.71V to 3.465V • Dual output common mode voltage operation: – Output common mod

文件：2.44589 Mbytes 页数：46 Pages

TI

德州仪器

LMK1D1204P Pin-Controlled OE Low Additive Jitter LVDS Buffer

1 Features • High-performance LVDS clock buffer family with 2 inputs and 4 outputs (2:4) • Output frequency up to 2 GHz • Hardware pins for individual output enable/disable • Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5% • Low additive jitter:

文件：1.17422 Mbytes 页数：32 Pages

TI

德州仪器

LMK1D210x Low Additive Jitter LVDS Buffer

文件：3.45386 Mbytes 页数：37 Pages

TI

德州仪器

丝印：LMK1D2108；Package：VQFN；LMK1D210x Low Additive Jitter LVDS Buffer

文件：3.45386 Mbytes 页数：37 Pages

TI

德州仪器

丝印：LMK1D2108；Package：VQFN；LMK1D210x Low Additive Jitter LVDS Buffer

文件：3.45386 Mbytes 页数：37 Pages

TI

德州仪器

Dual bank 8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer

The LMK1D210x clock buffer distributes two clock inputs (IN0 and IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0 to OUT15) in the LMK1D2108 and 12 pairs of clock outputs (OUT0 to OUT11) in the LMK1D2106 with minimum skew for clock distribution. Each buffer block consists of one • High-performance LVDS clock buffer family: up to 2 GHz \n• Dual 1:8 differential buffer\n• Supply voltage: 1.71 V to 3.465 V\n• Very low propagation delay: \n• High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1\n• Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML signal;

TI

德州仪器

LMK1D210xL Ultra Low Additive Jitter LVDS Buffer

1 Features • High-performance LVDS clock buffer family: up to 2GHz – Dual 1:2 differential buffer – Dual 1:4 differential buffer – Dual 1:6 differential buffer – Dual 1:8 differential buffer • Supply voltage: 1.71V to 3.465V • Dual output common mode voltage operation: – Output common mod

文件：2.47174 Mbytes 页数：46 Pages

TI

德州仪器

LMK1D210xL Ultra Low Additive Jitter LVDS Buffer

1 Features • High-performance LVDS clock buffer family: up to 2GHz – Dual 1:2 differential buffer – Dual 1:4 differential buffer – Dual 1:6 differential buffer – Dual 1:8 differential buffer • Supply voltage: 1.71V to 3.465V • Dual output common mode voltage operation: – Output common mod

文件：2.47737 Mbytes 页数：46 Pages

TI

德州仪器