丝印：LMK04100；Package：WQFN；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

文件：926.89 Kbytes 页数：56 Pages

TI

德州仪器

丝印：LMK04100；Package：WQFN；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

文件：926.89 Kbytes 页数：56 Pages

TI

德州仪器

丝印：LMK04100；Package：WQFN；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

文件：926.89 Kbytes 页数：56 Pages

TI

德州仪器

丝印：LMK04100；Package：WQFN；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

文件：926.89 Kbytes 页数：56 Pages

TI

德州仪器

丝印：LMK04100；Package：WQFN；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

文件：926.89 Kbytes 页数：56 Pages

TI

德州仪器

丝印：LMK04100；Package：WQFN；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

文件：926.89 Kbytes 页数：56 Pages

TI

德州仪器

具有级联 PLL 的精密时钟调节器时钟抖动消除器

The LMK04100 family of precision clock conditioners provides jitter cleaning, clock multiplication and distribution without the need for high-performance VCXO modules. When connected to a recovered system reference clock and a VCXO, the device generates 5 low jitter clocks in LVCMOS, LVDS, or LVPECL • Cascaded PLLatinum PLL Architecture \n• PLL1Redundant Reference Inputs Loss of Signal DetectionAutomatic and Manual Selection of Reference Clock Input\n• PLL2Phase Detector Rate up to 100 MHzInput Frequency-DoublerIntegrated VCO\n \n• Outputs \n• LVPECL/2VPECL, LVDS, and LVCMOS Formats\n• Support ;

TI

德州仪器

LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

文件：926.89 Kbytes 页数：56 Pages

TI

德州仪器

Family Clock Jitter Cleaner

文件：1.20015 Mbytes 页数：52 Pages

TI

德州仪器

Precision Clock Conditioner with Dual PLLs and Integrated VCO

文件：1.7294 Mbytes 页数：47 Pages

TI

德州仪器