FLEXIMARK® Wrapping label LCK

文件：924.88 Kbytes 页数：4 Pages

LAPP

缆普

Low-Voltage HSTL Differential Clock

General Description The LCK4801 is a low-voltage, 3.3 V HSTL differential clock synthesizer. The LCK4801 supports two differential HSTL output pairs with frequencies from 336 MHz to 1 GHz. The clock is designed to support single and multiple processor systems that require HSTL differential inputs

文件：160.93 Kbytes 页数：10 Pages

agere

Low-Voltage PECL Differential Clock

General Description The LCK4802 is a low-voltage, 3.3 V PECL differential clock synthesizer. The LCK4802 supports two differential PECL output pairs with frequencies from 336 MHz to 1 GHz. The clock is designed to support single and multiple processor systems that require PECL differential inputs

文件：156.72 Kbytes 页数：10 Pages

agere

Low-Voltage PLL Clock Driver

Description The LCK4950 is a PLL-based clock driver device intended for high-performance clock tree designs. The LCK4950 is 3.3 V compatible with output frequencies of up to 180 MHz and output skews of 200 ps. The LCK4950 can accommodate the most demanding tree designs by employing a fully differ

文件：215.76 Kbytes 页数：16 Pages

agere

Low-Voltage PLL Clock Driver

Description The LCK4953 is a PLL-based clock driver device intended for high-performance clock tree designs. The LCK4953 is 3.3 V compatible with output frequencies of up to 130 MHz and output skews of 75 ps. The LCK4953 can meet the most demanding timing requirements and employs on-chip voltage

文件：98.7 Kbytes 页数：6 Pages

agere

Low-Voltage PLL Clock Driver

文件：126.32 Kbytes 页数：10 Pages

agere

Low-Voltage PLL Clock Driver

文件：126.32 Kbytes 页数：10 Pages

agere

Low-Voltage PLL Clock Driver

文件：126.32 Kbytes 页数：10 Pages

agere

Low-Voltage PLL Clock Driver

文件：248.17 Kbytes 页数：20 Pages

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Low-Voltage PLL Clock Driver

文件：295.3 Kbytes 页数：16 Pages

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