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ISPLSI5256VE-125LT100中文资料PDF规格书
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ISPLSI5256VE-125LT100规格书详情
ispLSI 5000VE Description
The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs.
Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device.
Features
• Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 12000 PLD Gates / 256 Macrocells
— Up to 144 I/O Pins
— 256 Registers
— High-Speed Global Interconnect
— SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc.
— PCB Efficient Ball Grid Array (BGA) Package Options
— Interfaces with Standard 5V TTL Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 165 MHz Maximum Operating Frequency
— tpd = 6.0 ns Propagation Delay
— TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100 IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with Single Level Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and Registered Functions
— Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks
— Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options
— Four Global Product Term Output Enables, Two Global OE Pins and One Product Term OE per Macrocell
产品属性
- 型号:
ISPLSI5256VE-125LT100
- 功能描述:
CPLD - 复杂可编程逻辑器件
- RoHS:
否
- 制造商:
Lattice
- 存储类型:
EEPROM
- 大电池数量:
128
- 最大工作频率:
333 MHz
- 延迟时间:
2.7 ns
- 可编程输入/输出端数量:
64
- 工作电源电压:
3.3 V
- 最大工作温度:
+ 90 C
- 最小工作温度:
0 C
- 封装/箱体:
TQFP-100
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
LATTICE |
2023+ |
SMD |
19551 |
安罗世纪电子只做原装正品货 |
询价 | ||
LATTICE |
1950+ |
QFP |
6852 |
只做原装正品现货!或订货假一赔十! |
询价 | ||
LATTE/莱迪斯 |
23+ |
NA/ |
209 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
询价 | ||
LATTICE |
2138+ |
QFP |
8960 |
专营BGA,QFP原装现货,假一赔十 |
询价 | ||
LatticeSemiconductorCorp |
23+ |
100-TQFP(14x14) |
66800 |
优势价格原装正品 |
询价 | ||
Lattice Semiconductor Corporat |
23+ |
100-LQFP |
11200 |
主营:汽车电子,停产物料,军工IC |
询价 | ||
LATTICE/莱迪斯 |
2022 |
TQFP100 |
80000 |
原装现货,OEM渠道,欢迎咨询 |
询价 | ||
LATTICE/莱迪斯 |
QFP |
265209 |
假一罚十原包原标签常备现货! |
询价 | |||
LATTICE/莱迪斯 |
22+ |
TQFP-100 |
3000 |
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、 |
询价 | ||
Lattice |
17+ |
6200 |
100%原装正品现货 |
询价 |