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ISPLSI5256VE-100LT100I中文资料莱迪思数据手册PDF规格书
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ISPLSI5256VE-100LT100I规格书详情
ispLSI 5000VE Description
The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs.
Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device.
特性 Features
• Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 12000 PLD Gates / 256 Macrocells
— Up to 144 I/O Pins
— 256 Registers
— High-Speed Global Interconnect
— SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc.
— PCB Efficient Ball Grid Array (BGA) Package Options
— Interfaces with Standard 5V TTL Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 165 MHz Maximum Operating Frequency
— tpd = 6.0 ns Propagation Delay
— TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100 IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with Single Level Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and Registered Functions
— Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks
— Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options
— Four Global Product Term Output Enables, Two Global OE Pins and One Product Term OE per Macrocell
产品属性
- 型号:
ISPLSI5256VE-100LT100I
- 功能描述:
CPLD - 复杂可编程逻辑器件
- RoHS:
否
- 制造商:
Lattice
- 存储类型:
EEPROM
- 大电池数量:
128
- 最大工作频率:
333 MHz
- 延迟时间:
2.7 ns
- 可编程输入/输出端数量:
64
- 工作电源电压:
3.3 V
- 最大工作温度:
+ 90 C
- 最小工作温度:
0 C
- 封装/箱体:
TQFP-100
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Lattice Semiconductor Corporat |
24+ |
100-TQFP(14x14) |
56200 |
一级代理/放心采购 |
询价 | ||
Lattice |
2318+ |
QFP-100 |
4980 |
Lattice全系列进口原装特价 |
询价 | ||
LATTICE |
2015+ |
TQFP |
19889 |
一级代理原装现货,特价热卖! |
询价 | ||
LATTICE |
24+ |
TQFP1414 |
5825 |
公司原厂原装现货假一罚十!特价出售!强势库存! |
询价 | ||
LATTICE |
23+ |
QFP |
7000 |
询价 | |||
LATTICE |
24+ |
QFP |
6980 |
原装现货,可开13%税票 |
询价 | ||
Lattice |
17+ |
6200 |
100%原装正品现货 |
询价 | |||
Lattice Semiconductor Corporat |
2022+ |
100-TQFP(14x14) |
38550 |
全新原装 支持表配单 中国著名电子元器件独立分销 |
询价 | ||
Lattice Semiconductor Corporat |
21+ |
100-LQFP |
90 |
100%进口原装!长期供应!绝对优势价格(诚信经营) |
询价 | ||
LATTICE |
18+ |
TQFP |
25492 |
全新原装现货,可出样品,可开增值税发票 |
询价 |


