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IS61NLP12836EC-200B3

128K x36/32 and 256K x18 4Mb, ECC, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件:2.41096 Mbytes 页数:40 Pages

ISSI

矽成半导体

IS61NLP12836EC-200B3I

128K x36/32 and 256K x18 4Mb, ECC, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件:2.41096 Mbytes 页数:40 Pages

ISSI

矽成半导体

IS61NLP12836EC-200B3L

128K x36/32 and 256K x18 4Mb, ECC, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件:2.41096 Mbytes 页数:40 Pages

ISSI

矽成半导体

IS61NLP12836EC-200B3LI

128K x36/32 and 256K x18 4Mb, ECC, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件:2.41096 Mbytes 页数:40 Pages

ISSI

矽成半导体

IS61NLP12836EC-200TQL

128K x36/32 and 256K x18 4Mb, ECC, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件:2.41096 Mbytes 页数:40 Pages

ISSI

矽成半导体

IS61NLP12836EC-200TQLI

128K x36/32 and 256K x18 4Mb, ECC, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件:2.41096 Mbytes 页数:40 Pages

ISSI

矽成半导体

IS61NLP12836EC-250B2

128K x36/32 and 256K x18 4Mb, ECC, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件:2.41096 Mbytes 页数:40 Pages

ISSI

矽成半导体

IS61NLP12836EC-250B2I

128K x36/32 and 256K x18 4Mb, ECC, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件:2.41096 Mbytes 页数:40 Pages

ISSI

矽成半导体

IS61NLP12836EC-250B2L

128K x36/32 and 256K x18 4Mb, ECC, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件:2.41096 Mbytes 页数:40 Pages

ISSI

矽成半导体

IS61NLP12836EC-250B2LI

128K x36/32 and 256K x18 4Mb, ECC, PIPELINE NO WAIT STATE BUS SYNCHRONOUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usin

文件:2.41096 Mbytes 页数:40 Pages

ISSI

矽成半导体

技术参数

  • Organization:

    128Kx36

  • Product Type:

    No-Wait Pipeline

  • VccQ:

    2.5V/3.3V

  • Speed (MHz):

    250200

  • tKQ(ns):

    2.6

  • Package Pins:

    BGA(119)

  • Temperature Grade:

    C

  • Status:

    Prod

供应商型号品牌批号封装库存备注价格
ISSI
22+
TQFP
5000
全新原装现货!自家库存!
询价
INTEGRATEDSI
05+
原厂原装
4981
只做全新原装真实现货供应
询价
ISSI
16+
TQFP
2500
进口原装现货/价格优势!
询价
ISSI
23+
119-BGA(14x22)
1389
专业分销产品!原装正品!价格优势!
询价
ISSI
24+
QFP
5825
公司原厂原装现货假一罚十!特价出售!强势库存!
询价
ISSI
25+
QFP
138
百分百原装正品 真实公司现货库存 本公司只做原装 可
询价
ISSI
25+
QFP
4500
原装正品!公司现货!欢迎来电!
询价
ISSI
23+
BGAQFP
8659
原装公司现货!原装正品价格优势.
询价
ISSI
25+23+
TQFP100
20414
绝对原装正品全新进口深圳现货
询价
ISSI
23+
100-TQFP
65480
询价
更多IS61NLP12836供应商 更新时间2025-11-24 16:10:00