Auto refresh and Self refresh

文件：1.09752 Mbytes 页数：37 Pages

ISSI

矽成半导体

Auto refresh and Self refresh

ISSI

矽成半导体

8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and

文件：763.31 Kbytes 页数：32 Pages

ISSI

矽成半导体

8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and

文件：763.31 Kbytes 页数：32 Pages

ISSI

矽成半导体

8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and

文件：763.31 Kbytes 页数：32 Pages

ISSI

矽成半导体

8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and

文件：763.31 Kbytes 页数：32 Pages

ISSI

矽成半导体

8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and

文件：763.31 Kbytes 页数：32 Pages

ISSI

矽成半导体

8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and

文件：763.31 Kbytes 页数：32 Pages

ISSI

矽成半导体

8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and

文件：763.31 Kbytes 页数：32 Pages

ISSI

矽成半导体

8Mx32, 16Mx16, 32Mx8 256Mb DDR SDRAM

FEATURES • VDD and VDDQ: 2.5V ± 0.2V • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and

文件：763.31 Kbytes 页数：32 Pages

ISSI

矽成半导体