IS42S16800A1-7TL中文资料8Meg x 16 128-MBIT SYNCHRONOUS DRAM数据手册ISSI规格书

描述 Description

OVERVIEW
ISSI's 128Mb Synchronous DRAM  achieves high-speed data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows.FEATURES
• Clock frequency: 143 MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Power supply VDD VDDQ
  IS42S16800A1 3.3V 3.3V
• LVTTL interface
• Programmable burst length – (1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CASlatency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Lead-free Availability

特性 Features

• Clock frequency: 143 MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Power supply VDD VDDQ
  IS42S16800A1 3.3V 3.3V
• LVTTL interface
• Programmable burst length – (1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/Interleave
• Auto Refresh (CBR)
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CASlatency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Lead-free Availability