品牌：TI
批号：17+
数量:10000
封装:BGA
价格:面议
说明：全新原装现货，可出样品
IC特征：1 Digital Media System-on-Chip (DMSoC)
1.1 Features
TMS320DM6441
Digital Media System-on-Chip
www.ti.com SPRS359D–SEPTEMBER 2006–REVISED MARCH 2008
(Flexible RAM/Cache Allocation)
• High-Performance Digital Media SoC
– C64x+™ DSP Clock Rate • ARM926EJ-S Core
• 405-MHz – Support for 32-Bit and 16-Bit (Thumb Mode)
(Max) at 1.05 V or 513-MHz
(Max) at 1.2 V Instruction Sets
– ARM926EJ-S™ Clock Rate – DSP Instruction Extensions and Single
• 202.5-MHz (Max) at 1.05 V or 256-MHz Cycle MAC
(Max) at 1.2 V – ARM Jazelle Technology
– Eight 32-Bit C64x+ Instructions/Cycle – Embedded ICE-RT™ Logic for Real-Time
Debug
– 4752 C64x+ MIPS
– Fully Software-Compatible With C64x / • ARM9 Memory Architecture
ARM9™ – 16K-Byte Instruction Cache
• Advanced Very-Long-Instruction-Word (VLIW) – 8K-Byte Data Cache
TMS320C64x+™ DSP Core – 16K-Byte RAM
– Eight Highly Independent Functional Units – 8K-Byte ROM
• Six ALUs (32-/40-Bit), Each Supports • Embedded Trace Buffer™ (ETB11™) With 4KB
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Memory for ARM9 Debug
Arithmetic per Clock Cycle
• Endianness: Little Endian for ARM and DSP
• Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
• Video Processing Subsystem
Cycle or Eight 8 x 8-Bit Multiplies – Front End Provides:
(16-Bit
Results) per Clock Cycle • CCD and CMOS Imager Interface
– Load-Store Architecture With Non-Aligned • BT.601/BT.656 Digital YCbCr 4:2:2
Support (8-/16-Bit) Interface
– 64 32-Bit General-Purpose Registers • Preview Engine for Real-Time Image
– Instruction Packing Reduces Code Size Processing
– All Instructions Conditional • Glueless Interface to Common Video
Decoders
– Additional C64x+™ Enhancements
• Histogram Module
• Protected Mode Operation
• Auto-Exposure, Auto-White Balance,
• Exceptions Support for Error Detection
and Auto-Focus Module
and Program Redirection
• Resize Engine
• Hardware Support for Modulo Loop
Operation – Resize Images From 1/4x to 4x
– Separate Horizontal/Vertical Control
• C64x+ Instruction Set Features
– Byte-Addressable • Video Processing Subsystem (Continued)
(8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection – Back End Provides:
– Bit-Field Extract, Set, Clear • Hardware On-Screen Display (OSD)
– Normalization, Saturation, Bit-Counting • Four 54-MHz DACs for a Combination of
– Compact 16-Bit Instructions – Composite NTSC/PAL Video
– Additional Instructions to Support Complex – Luma/Chroma Separate Video
Multiplies (S-video)
– Component (YPbPr or RGB) Video
• C64x+ L1/L2 Memory Architecture
(Progressive)
– 32K-Byte L1P Program RAM/Cache (Direct
• Digital Output
Mapped)
– 8-/16-bit YUV or up to 24-Bit RGB
– 80K-Byte L1D Data RAM/Cache (2-Way
– HD Resolution
Set-Associative)
– Up to Two Video Windows
– 64K-Byte L2 Unified Mapped RAM/Cache
联系人:程小姐
手机:15919480276
电话:0755- 21015360 & 23038182
传真:0755-23038182
地址:深圳市福田区振华路海外装饰大厦综合大楼2栋B段4楼4014B-33C
