本公司最新整理TI，DSP热搜产品型号，产品图片，产品特性，产品PDF独家提供！
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以下是TI，DSP热搜新品型号：
66AK2L06
66AK2H14
66AK2H12
66AK2H06
66AK2G02
66AK2G01
66AK2E05
66AK2E02
TMS320VC5510A
TMS320VC5509A
TMS320VC5507
TMS320VC5506
TMS320VC5503
TMS320VC5502
TMS320VC5501
TMS320C5545
TMS320C5535
TMS320C5534
TMS320C5533
TMS320C5532
TMS320C5517
TMS320C5515
TMS320C5514
TMS320C5505
TMS320C5504
SM320VC5510A-HIREL
SM320VC5510A-EP
SM320VC5507-EP
TMS320C6678
TMS320C6674
TMS320C6672
TMS320C6671
TMS320C6670
TMS320C6657
TMS320C6655
TMS320C6654
TMS320C6652
SM320C6678-HIREL
TMS320C6748
TMS320C6747
TMS320C6746
TMS320C6745
TMS320C6743
TMS320C6742
SM320C6748-HIREL
TMS320DM8168
TMS320DM8167
TMS320DM8165
TMS320DM8148
TMS320DM8147
TMS320DM8127
TMS320DM648
TMS320DM647
TMS320DM6467T
TMS320DM6437
TMS320DM6435
TMS320DM6433
TMS320DM6431
TMS320DM369
TMS320DM368
TMS320DM365
SM320DM6446-HIREL
SM320DM355-EP
DMVA3
DM505M
DM388
DM385
DM383
DM3730
DM3725
OMAP3530-HIREL
OMAP3525-HIREL
OMAP3525
SMOMAPL138B-HIREL
OMAPL138B-EP
OMAPL137-HT
OMAP-L138
OMAP-L137
OMAP-L132
TMS320VC5441
TMS320VC5416
TMS320VC5410A
TMS320VC5409A
TMS320VC5407
TMS320VC5404
TMS320VC5402A
TMS320VC5402
TMS320VC5401
SMJ320VC5416
SM320VC5421-EP
SM320VC5416-EP
TMS320C6727B
TMS320C6727
TMS320C6726B
TMS320C6722B
TMS320C6720
TMS320C6713B
TMS320C6712D
TMS320C6711D
TMS320C6701
TMS320C6474
TMS320C6472
TMS320C6457
TMS320C6455-850
TMS320C6455-1000
TMS320C6455-720
TMS320C6455-1200
TMS320C6454-1000
TMS320C6452-900
TMS320C6424-400
TMS320C6424-500
TMS320C6424-600
TMS320C6424-700
TMS320C6421-700
TMS320C6421-500
TMS320C6421-600
TMS320C6421-400
TMS320C6418-500
TMS320C6418-600
TMS320C6416T-720
TMS320C6416T-1000
TMS320C6416T-600
TMS320C6416-7E3
TMS320C6416-5E0
TMS320C6416-6E3
TMS320C6415T-850
TMS320C6415T-720
TMS320C6415T-600
TMS320C6415T-1000
TMS320C6415-6E3
TMS320C6415-7E3
TMS320C6415-5E0
TMS320C6414T-1000
TMS320C6414T-850
TMS320C6414T-720
TMS320C6414T-600
TMS320C6414-5E0
TMS320C6414-7E3
TMS320C6414-6E3
TMS320C6413-500
TMS320C6412-600
TMS320C6412-500
TMS320C6412-720
TMS320C6411-300
TMS320C6205
TMS320C6204
TMS320C6203B
TMS320C6202B
TMS320C6201
SMV320C6727B-SP
SMJ320C6701-SP
SMJ320C6701
SMJ320C6203
SMJ320C6201B
SM32C6416T-EP
SM320DM642-HIREL
SM320C6727B-EP
SM320C6727B
SM320C6712D-EP
SM320C6711D-EP
SM320C6701-EP
SM320C6701
SM320C6472-HIREL
SM320C6424-EP
SM320C6415-EP
SM320C6415
SM320C6201B
SM320C6201-EP
SMJ320C80
SMJ320C40
SMJ320C30KGD
SMJ320C30
SMJ320C25
SM320VC33-EP
SM320C80
SM320C40
SM320C30
产品特性：
Highest-Performance Fixed-Point DSPs
1.67-/1.39-/1.17-/1-ns Instruction Cycle
600-/720-/850-MHz, 1-GHz Clock Rate
Eight 32-Bit Instructions/Cycle
Twenty-Eight Operations/Cycle
4800, 5760, 6800, 8000 MIPS
Fully Software-Compatible With C62x™
C6414/15/16 Devices Pin-Compatible
Extended Temperature Devices Available
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
Non-Aligned Load-Store Architecture
64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Instruction Set Features
Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
VelociTI.2™ Increased Orthogonality
VCP [C6416T Only]
Supports Over 833 7.95-Kbps AMR
Programmable Code Parameters
TCP [C6416T Only]
Supports up to 10 2-Mbps or 60 384-Kbps 3GPP (6 Iterations)
Programmable Turbo Code and Decoding Parameters
L1/L2 Memory Architecture
128K-Bit (16K-Byte) L1P Program Cache(Direct Mapped)
128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
Two External Memory Interfaces (EMIFs)
One 64-Bit (EMIFA), One 16-Bit (EMIFB)
Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
1280M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
Host-Port Interface (HPI)
User-Configurable Bus Width (32-/16-Bit)
32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415T/C6416T]
Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O
Four-Wire Serial EEPROM Interface
PCI Interrupt Request Under DSP Program Control
DSP Interrupt Via PCI I/O Cycle
Three Multichannel Buffered Serial Ports
Direct Interface to T1/E1, MVIP, SCSA Framers
Up to 256 Channels Each
ST-Bus-Switching-, AC97-Compatible
Serial Peripheral Interface (SPI) Compatible (Motorola™)
Three 32-Bit General-Purpose Timers
UTOPIA [C6415T/C6416T]
UTOPIA Level 2 Slave ATM Controller
8-Bit Transmit and Receive Operations up to 50 MHz per Direction
User-Defined Cell Format up to 64 Bytes
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
532-Pin Ball Grid Array (BGA) Package (GLZ and ZLZ Suffixes), 0.8-mm Ball Pitch
0.09-µm/7-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.1-V Internal (600 MHz)
3.3-V I/Os, 1.2-V Internal (720/850 MHZ, 1 GHz)
C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorla is a registered trademark of the Motorola, Inc.
新品描述：
The TMS320C64x™ DSPs (including the TMS320C6414T, TMS320C6415T, and TMS320C6416T devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C64x™ (C64x™) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for wireless infrastructure applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.
With performance of up to 8000 million instructions per second (MIPS) at a clock rate of 1 GHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x™ DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x. DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI™ architecture. The C64x can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 4000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 8000 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.
The C6416T device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 833 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to sixty 384-Kbps or ten 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.
The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port [C6415T/C6416T only]; three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415T/C6416T only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.
The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows. debugger interface for visibility into source code execution.
TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Other trademarks are the property of their respective owners.
Throughout the remainder of this document, the TMS320C6414T, TMS320C6415T, and TMS320C6416T shall be referred to as TMS320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414T, C6415T, or C6416T.
These C64x™ devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name.
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