品牌；CSR
型号：CSRS3661B00-IBBO-R
封装：BGA
包装：2000
年份：1601+
数量：160000
CSR大陆授权代理商.
深圳市东兴微电子有限公司
联系人：张燕玲
电话：13641440131
qq：851574834
1. 产品描述：
蓝牙V4.0版本规范；
功率级别II级；
超低功耗，微安级工作电流
超低电压供电，可使用3V钮扣电池
内置521K字节可擦除存储器
多种引出接口：PIO/UART/SPI/AIO/I?C
监视时钟功能
极小的表面贴片封装：12Χ12Χ2.5mm
带屏蔽罩，有效减小干扰
RoHS无铅生产工艺
2. 应用领域：
健身器材设备，如跑步机，健身器等
医疗器械设备，如脉博测量计，心率计等
家用休闲设备，如遥控器，玩具等
办公用品设备，如打印机，扫描仪等
商业设备，如收银机，二维码扫描器等
手机外设配件，如手机防丢器等
汽车设备，如汽车维修仪等
其它人机交互设备l
CSRG3000介绍：
CSR 发表针对超低功耗连结装置需求所设计的首款单模单芯片蓝牙低功耗平台 CSRG3000和 CSRG3000。新 CSR uEnergy 平台在一颗单芯片上提供所有必要技术，以协助开发蓝牙低功耗产品，包括射频、基频、微控制器、通过认证的 BluEtooth v4.0 堆栈、以及使用者自订应用。 CSR uEnergy 蓝牙低功耗平台将让以往受限于功率消耗、尺寸和其它无线标准等复杂应用实现超低功耗连接性。
CSR uEnergy 平台已实施最佳化设计，专门使用于支持蓝牙低功耗功能，协助开发小型、成本效益且能源效率的产品。 CSR 芯片只需要一颗单一钮扣型电池就可以使用多年，而且能够被建置到简单的传感器中，例如计步器、心律监测器或者车钥匙链，以及较复杂的低功耗装置，例如可控 制和显示行动电话信息的手表。该平台提供单模芯片，能够与 CSR 的双模芯片相辅相成，进而构成完整的蓝牙低功耗方案。
Features SiRFatlasVI™
■ ADVANCED.html" target="_blank" title="ADVANCED">ADVANCED ARM Cortex-A9 CPU core with Neon
and high-speed MEMORY bus:
■ 32KB I / 32KB D cache
■ 800MHZ at 2000DMIPS, 1GHz at
2500DMIPS (through binning)
■ Advanced 3D accelerator supporting
OpenGL ES2.0
■ Navigation
■ GPS, GLONASS, Galileo and Compass ready
■ Navigation tracking: -162dBm
■ Reacquisition: -161dBm
■ AlwaysFix support
■ SiRFDRive1, SiRFDRive2, SiRFDiRect
support
■ 26MHz TCXO 2.5ppm, sharing with system
crystal
■ Pulse counter with direction indicator
■ Industry-leading GNSS engine that supports GPS,
Galileo, GLONASS and Compass
■ Two USB 2.0, one integrated with PHY, one with
external PHY
■ Wide range of RAM and NAND/MMC
■ Multiple communication port supported (UART/I2S/
SPI/I2C)
■ 13.4 x 12.6 x 1.16mm 0.65mm pitch 362-ball
FCBGA
■ Temperature range for Industrial grade part -40° C
to 85° C
Application Processor
Production Information
CSRS3661B00-IBBO-R
CSRS3662B00-IBBO-R
Issue 2
SiRFatlasVI
PCM
Radio
I2C
Multichannel
Codec
DDR3
SLC / MLC /
eMMC
UART
SDIO
GNSS
BB
I2C
VIP
UART
I2C VIP
UART
Stereo
Codec
SD
LCD
MCU
Bluetooth
CSR8311
Wi-Fi
CSR6030
TriG RF
HDMI
to
BT656
Video ADC
BT656
Aux 1, 2
Security IC
MIC_IN
SPKR_OUT
General Description
SiRFatlasVI is the latest generation application
processor from CSR’s multi-function SoC product
family. Designed around an advanced CPU core, highspeed
memory bus and advanced 3D accelerator,
SiRFatlasVI meets the needs of complicated
applications for modern multi-function devices that
require heavy concurrent applications and fluid user
experience.
Integrated with GPS baseband and analogue, this new
platform is designed to provide a cost-effective solution
for Automotive and Consumer markets.
SiRFatlasVI supports both mono and stereo audio input
and output. The hardware video post processor is
capable of colour space conversion and advanced deinterlacing
Peripherals and Interfaces
Memory
■ 16-bit memory controller supporting:
■ DDR3 at 400MHz
■ LPDDR2 at 333MHz
■ Up to 512MB
NAND
■ SLC/MLC/TLC 512B/2KB/4KB/8KB/16KB page,
64/128/192/256 pages per block
■ 8-bit data width with 12-bit/24-bit/40-bit/60-bit ECC
engine
■ eMMC 4.4 support
■ Supports DDR (100Mbps) and SDR modes
■ Randomiser
Audio Integration
■ Mono and stereo audio input and output
■ I2S and AC97 support
■ Audio path control, mixer and loopback
■ Audio in/out gain control
■ CVC for AEC and NS
Connectivity
■ 3 dedicated UART ports, two with hardware flow
control and DMA
■ 2 USP ports for I2S, SPI, PCM or UART mode
■ 2 I2C interfaces
■ 2 SPI interfaces
■ 2 USB 2.0 HS OTG: one with on-chip PHY that
supports UART/USB switch, and another with ULPI
which can be used as GPIOs when free
■ 4-wire touch-screen controller integrated
Storage
■ 2 port 8-bit eMMC 4.4 port with SDR/DDR mode
muxed with NAND I/F
■ 1 port 4-bit SDXC port primarily for memory card
■ 1 port 4-bit SDIO port for peripheral connection
■ 1 port 1-bit SD interface for TriG RF packetised
Security
■ Secure boot
■ 128-bit AES
■ SHA-256
■ Lockable JTAG
■ Per-chip ID
Package Options
■ Industrial: 13.4 x 12.6 x 1.16mm FCBGA 0.65mm
pitch
Display, Graphics and Multimedia
■ 2D only, supports:
■ ARGB8888, ABGR8888 and RGB565 for source
surface format in hardware BLT
■ ARGB8888 and RGB565 for destination surface
format in hardware BLT
■ Constant alpha blend, per-pixel alpha blend from
source ARGB surface and both constant alpha
and per-pixel alpha blend to destination surface
in hardware BLT
■ Hardware clips the destination rectangle before
hardware BLT
■ Hardware supports ROP3 (pattern surface
support to 8 x 8 x 32) in BLT
■ 90, 180 or 270 degree image rotation hardware
BLT from one surface to another
■ Mirror the image in horizontal or vertical direction
when hardware BLT in non-overlap mode
■ Command buffer to queue the hardware BLT
commands
■ Fence command to sync with other modules
■ Source/destination color key support when
hardware BLT
■ 2D/3D Hardware Graphic supports:
■ OpenGL ES 1.1 and 2.0
■ OpenVG 1.1
■ Egl 1.4
■ GDI/Ddraw/Android UI
■ Display:
■ Resolution up to 1280 x 720
■ 16-bit/24-bit (RGB565/888) LCD interface
■ 16-bit ROM interface for serial panels
■ On-chip RGB to YUV hardware conversion and
interface to TV encoder (8-bit 4:2:2 or 16-bit
4:2:2)
■ Configurable 4 overlays
■ Global gamma table support
■ Backlight-scaling under video playback
■ Multimedia:
■ Hardware Video Post Processor capable of color
space conversion and advanced de-interlacing
(scaling 1/8 to 8)
■ Independent brightness/contrast control
■ 8-bit VIP supporting up to 5M pixel camera and
CCIR656 input
■ Left-right mirror function to support instant
backview
2 RISC Subsystem
The RISC subsystem contains:
■ ARM Cortex-A9 MP with Neon
■ 32KB I-cache
■ 32KB D-cache
■ RISC interface
2.1 ARM Cortex-A9 MP with NEON
ARM Cortex-A9 MP with NEON consists of:
■ A Cortex-A9 processor
■ A Snoop Control Unit (SCU) that ensures coherency within cluster
Features include:
■ 5-stage integer pipeline with branch prediction and 3-stage prefetch unit
■ ARM, Thumb-2 and Thumb-2EE instruction set support, Jazelle DBX hardware acceleration
■ TrustZone security extensions
■ Harvard level 1 memory system with:
■ Memory management unit
■ 32KB I-cache
■ 32KB D-cache
■ VFPv3-D32 FPU with trapless execution
■ 2 64-bit AXI master interfaces
■ V7 debug architecture
For more information, see ARM Cortex-A9 documents on the ARM web site
RISC Interface
The RISC interface is an internal function block for converting the AXI Bus protocol to I/O bus.
Features include:
■ Bus protocol converts between AXI bus and I/O bus
■ Address mapping
■ Timeout:
■ Programmable timeout time
■ Terminates I/O bus transfer, returns zero for read operation
■ When timeout occurs, address and operation type are recorded
■ Timeout status can be software cleared
■ For debug, timeout status and address are not reset
■ When timeout occur, slave error response can return to CPU to cause data abort
■ Interrupt can be software masked and cleared
■ I/O bridge software reset
