freescale代理MC9S08DZ128 MPC5676
深圳市世联芯科技有限公司
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The 32-bit Qorivva MPC5676R microcontroller (MCU) built on Power Architecture® technology is Freescale’s first multicore device designed for advanced powertrain control applications. The Qorivva MPC5676R performs four to five times better than previous-generation MCU families, addressing advanced filtering and signal processing requirements of direct injection, advanced diesel, hybrid electric and full electric powertrain applications to meet extreme regulatory and environmental requirements.
The Qorivva MPC5676R MCU achieves significant performance benchmarks with dual 180 MHz processors, three second-generation, high-performance time processor units (eTPU2), 6 MB of on-chip flash, 128-channel timers (3 x eTPU2s and 1 x eMIOS), quad ADCs, 384 KB RAM (for data storage) and on-chip digital signal processing capable of knock detection without the requirement of additional external components.
The Qorivva MPC5676R MCU is fully compatible with the Qorivva MPC567xF MCU, allowing automakers to incorporate this new technology easily for applications that require increased performance or memory expansion. Offering customers a seamless migration allows design re-use, and helps to reduce overall design cost and speed time to market.
The MPC5600 family of devices is closely compatible with the MPC5500 families, while introducing new features coupled with high performance CMOS technology to provide substantial reduction of cost per feature and significant performance improvement. This document describes the features of the MPC5676R and highlights important electrical and physical characteristics of this device.
The two e200z7 host processor cores of the MPC5676R are compatible with the Power Architecture Book E architecture. They are 100% user-mode compatible (with floating point library) with the classic PowerPC instruction set. The Book E architecture has enhancements that improve the architecture’s fit in embedded applications. In addition to the standard and VLE Power Architecture instruction sets, this core has additional instruction support for digital signal processing (DSP).
The MPC5676R has two levels of memory hierarchy; separate 16K instruction and 16K data caches for each of two cores and 384KB of on-chip SRAM. 6MB of internal flash memory is provided. An external bus interface is also available for special packaged parts to support application development and calibration.
MPC5676主要特性和优势:
MPC5676R是采用Power Architecture®技术的32位多核Qorivva MCU,主要用在汽车动力总成系统. MPC5676R集成了两个180MHz处理器,三个第二代高性能时间处理器单元(eTPU2),6MB闪存,128路定时器(3 x eTPU2和1 x eMIOS),四个ADC,384KB RAM(数据存储)以及不需要外接元件进行爆震检测的信号处理电路.主要用在动力总成引擎控制,汽油直接注入,混合动力汽车, 爆震检测,传动控制等.本文介绍了MPC5676主要特性和优势,方框图以及Qorivva MPC567XEVB评估板主要组成与特性,以及相应电路图.
