FEATURES ? PC100- and PC133-compliant ? Fully synchronous; all signals registered on positive edge of system clock ? Internal pipelined operation; column address can be changed every clock cycle ? Internal banks for hiding row access/precharge ? Programmable burst lengths: 1, 2, 4, 8, or full page ? Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes ? Self Refresh Mode ? 64ms, 8,192-cycle refresh ? LVTTL-compatible inputs and outputs ? Single +3.3V ±0.3V power supply OPTIONS MARKING ? Configurations 128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4 64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16 ? WRITE Recovery ( tWR) tWR = “2 CLK” 1 A2 ? Plastic Package – OCPL 2 54-pin TSOP II (400 mil) TG ? Timing (Cycle Time) 7.5ns @ CL = 2 (PC133) -7E 7.5ns @ CL = 3 (PC133) -75 ? Self Refresh Standard None Low power L ? Operating Temperature Commercial (0 o C to +70 o C) None NOTE: 1. Refer to Micron Technical Note TN-48-05. 2. Off-center parting line. Part Number Example: MT48LC32M16A2TG-75
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