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RTD1185DA-GR
RTD1185DD-GR
FULL HD MULTI-FORMAT MULTIMEDIA
DECODER WITH HIGH-SPEED INTERFACES,
10/100/1000M ETHERNET, HDMI, AND DTV
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.3
28 October 2011
Track ID: CONF-2265-11
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
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Datasheet
Full HD Multi-Format Multimedia Decoder with High-Speed
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ii Track ID: CONF-2265-11 Rev. 1.3
COPYRIGHT
©2011 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
RTD1185 controller ICs.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision Release Date Summary
1.0 2010/10/20 First release.
1.1 2010/11/09 Revised ISO_1.0V parameters in Table 2, page 18.
1.2 2011/01/21 Revised section 7 Licenses, page 17.
Revised Figure 6 Power-On Sequence Timing Diagram, page 21.
Revised Table 5 POR Circuit Specification, page 21.
Revised section 15.1 Features, page 41.
Revised Table 28 Ordering Information, page 58.
1.3 2011/10/28 Revised RTD1185_Datasheet_Conf_1.2 to RTD1185DA_DD_Datasheet_Conf_1.3.
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iii Track ID: CONF-2265-11 Rev. 1.3
Realtek Confidential
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Full HD Multi-Format Multimedia Decoder with High-Speed
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1 Track ID: CONF-2265-11 Rev. 1.3
1. General Description
The RTD1185DA-GR/RTD1185DD-GR is a highly integrated SoC for Consumer Electronic products
requiring High Definition Media Playback, Wireless/Wired Networking, Mass Storage, and DTV
capabilities.
Main features of the RTD1185 include HD MPEG1/2/4/H.264 & HD JPEG Decoder, HD AVC/VC-1
Decoder, HD RM/RMVB Decoder, HD AVS Decoder, DTV Recording & Timeshifting, AV
Streaming/Transmission via Ethernet & WiFi, TV Encoder with CVBS/ YPbPr/SCART out, I
2
S, SPDIF
out, HDMI Transmitter and PHY, OTP (One-Time Programmable ROM), dual USB 2.0 Host or one
USB 2.0 Host/Device with dual port integrated PHY, NAND/NOR flash controller, SATA, PCI Express,
Card reader supporting SD and MMC, 10/100M Ethernet MAC and PHY, and 10/100/1000M Ethernet
MAC.
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2. Features
2.1. Hardware Features
„ System and Peripherals
‹ 500MHz MIPS24Kc processor
‹ Video engine with HW acceleration
‹ Audio engine with HW acceleration
‹ Supports up to 512MB DDR2/DDR3
SDRAM with 32-bit data interface
‹ Supports Serial NOR Flash with dual I/O
data interface
‹ Supports NAND Flash
‹ Boot-ROM and OTP (One-Time
Programmable ROM) for Secure-Boot
and Key storage
‹ Integrated SATA 2.0 MAC and PHY
‹ Integrated 10/100M Ethernet MAC and
PHY
‹ Integrated 10/100/1000M Ethernet MAC
‹ Integrated dual USB 2.0 High Speed
Host controller, or one Host/Device
controller, and Dual PHY
‹ Integrated PCI Express interface MAC
and PHY
‹ Supports SD and MMC Cards
‹ Supports UART/IrDA/I
2
C/GPIO/
EJTAG/VFD/RTC
„ Audio Interface and Function
‹ Built-in Audio DAC with 24-bit
resolution
‹ One 2-CH I
2
S interface for Audio output
‹ IEC-60958 (SPDIF) digital audio output
‹ 7.1 down-mix
‹ MPEG I Layer 1, 2, 3 (2-CH) and MPEG
II Layer 1, 2 (Multi-Channel)
‹ LPCM, ADPCM, FLAC, AAC, WAV,
and OGG Vorbis
‹ DTS HD Master Audio, Low Bit Rate
(LBR)
‹ Dolby® Digital Plus, TrueHD
‹ RA1/RA-cook/RA-lossless
‹ WMA/WMA Pro, Dolby® Digital AC3
and DTS® (Licensee Only)
„ Video Interface
‹ Two Parallel/Serial TS inputs for Digital
TV systems
‹ TV encoder with six 12-bit video D/A
converters
‹ NTSC and PAL TV systems
‹ Composite analog video outputs
‹ S-Video (Y/C) analog video outputs
‹ Component (YPbPr or RGB) analog
video output
‹ Simultaneous Composite, S-Video, and
YPbPr output
‹ Simultaneous SD/HD output
‹ VGA/XVGA/SVGA output
‹ HDMI version 1.3 transmitter with CEC
‹ Supports SCART output
‹ 3D De-interlacer
‹ Bitmap OSD
„ Video and Picture Function
‹ Supports 1 HD decoder
‹ MPEG1, VCD 1.0/2.0, SVCD
‹ Supports HD MPEG2 (up to MP@HL
1080p), ISO/IFO/VOB/TS
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‹ Supports HD MPEG4 SP/ASP
(720p/1080i/1080p), Xvid
‹ H.264 BP@L4.1, HP@L4.1
‹ WMV9/VC-1 AP@L3
‹ RealVideo 8/9/10, up to 1080@30P
‹ DivX3/4/5/6 (Licensee Only)
‹ AVS HD 1920x1080
‹ HD JPEG with unlimited resolution
(40M-pixel tested)
‹ Full-pixel JPEG decode with high
resolution zoom-in
‹ De-blocking/De-ringing Filter
‹ Video upscaling from SD to HD
(720p/1080i/1080p)
‹ Supports 24/30/36-bit deep color
„ Copy Protection
‹ CSS
‹ CGMS-A
‹ HDCP
‹ Microsoft DRM
‹ Secure Boot with OTP and embedded
boot-ROM
2.2. Software Features
„ Operating System: Linux
„ Media Browser and Player
„ Supports Subtitles
„ Photo slideshow with transition effects
„ Network applications
„ DTV function
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3. System Applications
„ HD Media Player
„ Digital Media Adaptor/Server
„ STB with PVR (Personal Video Recorder)
„ Networked Media Module for Embedded CE devices
3.1. Application Diagram
Figure 1. Application Diagram
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4. Block Diagram
MIPS24Kc
Peripheral
GPIO
UART
IR
I
2
C VFD Ctrl.
Timer Ctrl.
USB
Host &
Device
1000M
ETN
MAC
Flash
Ctrl.
DDR2/3
Ctrl.
HDMI
TV
Encoder
SPDIF Output I
2
S Output
10/100M
ETN MAC
& PHY
OTP
ROM
RTC
PLL
PCI-e
SATA
Card
Reader
TS Input
Audio
Engine
Video
Engine
Figure 2. Block Diagram
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5. Pin Assignments
5.1. Package Identification
DX in the model number indicates DA or DD model. Green package is indicated by the ‘G’ in GXXXX
(Figure 3).
A B C D E F G H J K L M N P R T U V W Y
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 3. Package Identification
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5.2. Pin Assignments (Bottom View)
Figure 4. Pin Assignments (Bottom View)
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6. Pin Descriptions
DI: Digital Input AI: Analog Input
DO: Digital Output AO: Analog Output
DB: Digital Bidirectional AB: Analog Bidirectional
GND: Ground PWR: Power Supply
Table 1. Pin Descriptions
Pin No. Pin Name I/O Description
UART0_RX DI UART 0 Receive Data Input A1
GPIO59 DB General Purpose IO 59
A2 N_FLASH DI NAND Flash Selection
SPDIF_OUT DO IEC958 (SPDIF) Output A3
IGPIO7 DB General Purpose IO 7
A4 PCIE_HSOP AO PCI Express TX+
A5 PCIE_HSIP AI PCI Express RX+
A6 RTC_XI AI 32.768kHz Crystal Oscillator Input
A7 XTLO AO 27MHz Crystal Oscillator Output
A8 VDAC_B AO Video B Channel DAC Output
A9 VDAC_GND GND Video DAC Ground
A10 REXT PWR External Reference Resistor
A11 VREF PWR Audio DAC Common Mode Voltage Output
A12 AO_L AO Audio DAC Output Left Channel
SPI_SI/SIO0 DB Serial Flash Data Input A13
GPIO0 DB General Purpose IO 0
I2C1_SCL DB I
2
C 1 Serial Clock Output A14
GPIO63 DB General Purpose IO 63
UART1_RX DI UART 1 Receive Data Input A15
GPIO57 DB General Purpose IO 57
A16 AO_LRCK DO I
2
S Word Select
A17 TP1_CLK DI Transport Stream 1 Input
TP1_DATA3 DI Transport Stream 1 Input (Parallel Mode Only)
A18
GPIO48 DB General Purpose IO 48
TP1_DATA6 DI Transport Stream 1 Input (Parallel Mode Only)
A19
GPIO51 DB General Purpose IO 51
A20 TP0_SYNC DI Transport Stream 0 Input
UART0_TX DO UART 0 Transmit Data Output B1
GPIO60 DB General Purpose IO 60
B2 GPIO6 DB General Purpose IO 6
B3 TESTMODE DI Select Test Mode
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Pin No. Pin Name I/O Description
B4 PCIE_HSON AO PCI Express TX-
B5 PCIE_HSIN AI PCI Express RX-
B6 RTC_XO AO 32.768kHz Crystal Oscillator Output
B7 XTLI AI 27MHz Crystal Oscillator Input
B8 VDAC_C AO Video C Channel DAC Output
B9 VDAC_F AO Video F Channel DAC Output
B10 VDAC_GND GND Video DAC Ground
B11 VRP PWR Audio DAC VREF+
B12 AO_R AO Audio DAC Output Right Channel
SPI_SCK DO Serial Flash Clock B13
GPIO1 DB General Purpose IO 1
I2C1_SDA DB I
2
C 1 Serial Data Signal B14
GPIO64 DB General Purpose IO 64
UART1_TX DO UART 1 Transmit Data Output B15
GPIO58 DB General Purpose IO 58
B16 AO_SD0 DO I
2
S Serial Data
B17 TP1_DATA0 DI Transport Stream 1 Input
TP1_DATA4 DI Transport Stream 1 Input (Parallel Mode Only)
B18
GPIO49 DB General Purpose IO 49
TP1_DATA7 DI Transport Stream 1 Input (Parallel Mode Only)
B19
GPIO52 DB General Purpose IO 52
B20 TP0_VALID DI Transport Stream 0 Input
EPHYCLK DO RTD1185 Output to External Giga PHY 25MHz Clock Input C1
GPIO88 DB General Purpose IO 88
ETN_LINK DO Link LED for ETN PHY C2
GPIO68 DB General Purpose IO 68
ETN_ACT DO RX/TX LED for ETN PHY C3
GPIO69 DB General Purpose IO 69
C4 PCIE_CLKP AO PCI Express Clock+
C5 PCIE_1.0V PWR PCI Express Power 1.0V
C6 RTC_3.3V PWR RTC Power 3.3V
C7 PLL_1.0V PWR PLL Power 1.0V
C8 ISO_1.0V PWR ISO Block Power 1.0V
C9 VDAC_E AO Video E Channel DAC Output
C10 VDAC_3.3V PWR Video DAC Power 3.3V
C11 VDAC_A AO Video A Channel DAC Output
C12 ADAC_GND GND Audio DAC Ground
SPI_CE# DO Serial Flash Chip Enable C13
GPIO2 DB General Purpose IO 2
C14 GPIO5 DB General Purpose IO 5
C15 AO_MCLK DO I
2
S 256x Clock to DAC
C16 TP1_SYNC DI Transport Stream 1 Input
TP1_DATA1 DI Transport Stream 1 Input (Parallel Mode Only)
C17
GPIO46 DB General Purpose IO 46
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Pin No. Pin Name I/O Description
TP1_DATA5 DI Transport Stream 1 Input (Parallel Mode Only)
C18
GPIO50 DB General Purpose IO 50
C19 TP0_CLK DI Transport Stream 0 Input
C20 TP0_DATA0 DI Transport Stream 0 Input
TXEN DO RGMII Transmit Enable D1
GPIO118 DB General Purpose IO 118
MDC DO Management Data Clock D2
GPIO86 DB General Purpose IO 86
MDIO DB Management Data Input/Output D3
GPIO8 DB General Purpose IO 8
D4 PCIE_CLKN AO PCI Express Clock-
D5 PCIE_GND GND PCI Express Ground
D6 PLL_3.3V PWR PLL Power 3.3V
D7 PLL_GND GND PLL Ground
D8 ISO_1.0V PWR ISO Block Power 1.0V
D9 VDAC_D AO Video D Channel DAC Output
D10 VDAC_3.3V PWR Video DAC Power 3.3V
D11 ADAC_GND GND Audio DAC Ground
D12 ADAC_3.3V PWR Audio DAC Power 3.3V
SPI_SO/SIO1 DI Serial Flash Data Output D13
GPIO3 DB General Purpose IO 3
D14 GPIO4 DB General Purpose IO 4
D15 AO_BCLK DO I
2
S Bit Clock
D16 TP1_VALID DI Transport Stream 1 Input
TP1_DATA2 DI Transport Stream 1 Input (Parallel Mode Only)
D17
GPIO47 DB General Purpose IO 47
TP0_DATA1 DI Transport Stream 0 Input (Parallel Mode Only)
D18
GPIO34 DB General Purpose IO 34
TP0_DATA2 DI Transport Stream 0 Input (Parallel Mode Only)
D19
GPIO35 DB General Purpose IO 35
TP0_DATA3 DI Transport Stream 0 Input (Parallel Mode Only)
D20
GPIO36 DB General Purpose IO 36
TXD0 DO RGMII Transmit Data E1
GPIO117 DB General Purpose IO 117
TXD1 DO RGMII Transmit Data E2
GPIO116 DB General Purpose IO 116
TXD2 DO RGMII Transmit Data E3
GPIO115 DB General Purpose IO 115
TXD3 DO RGMII Transmit Data E4
GPIO114 DB General Purpose IO 114
TP0_DATA4 DI Transport Stream 0 Input (Parallel Mode Only)
E17
GPIO37 DB General Purpose IO 37
TP0_DATA5 DI Transport Stream 0 Input (Parallel Mode Only)
E18
GPIO38 DB General Purpose IO 38
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Pin No. Pin Name I/O Description
TP0_DATA6 DI Transport Stream 0 Input (Parallel Mode Only)
E19
GPIO39 DB General Purpose IO 39
TP0_DATA7 DI Transport Stream 0 Input (Parallel Mode Only)
E20
GPIO40 DB General Purpose IO 40
RXD2 DI RGMII Receive Data F1
GPIO66 DB General Purpose IO 66
RXD3 DI RGMII Receive Data F2
GPIO65 DB General Purpose IO 65
RXC DI RGMII Receive Clock F3
GPIO9 DB General Purpose IO 9
TXC DO RGMII Transmit Clock F4
GPIO113 DB General Purpose IO 113
F17 GND PWR Digital Ground
F18 GND PWR Digital Ground
F19 1.8V/1.5V PWR DDR2 or DDR3 Power
F20 1.8V/1.5V PWR DDR2 or DDR3 Power
RXDV DI RGMII Receive Data Valid G1
GPIO87 DB General Purpose IO 87
RXD0 DI RGMII Receive Data G2
GPIO70 DB General Purpose IO 70
RXD1 DI RGMII Receive Data G3
GPIO67 DB General Purpose IO 67
G4 GND PWR Digital Ground
G17 DDR2_DQ26/DDR3_DQ30 DB DDR2 Data Bit 26 or DDR3 Data Bit 30
G18 DDR2_DQ29/DDR3_DQ26 DB DDR2 Data Bit 29 or DDR3 Data Bit 26
G19 DDR2_DQ18/DDR3_DQ23 DB DDR2 Data Bit 18 or DDR3 Data Bit 23
G20 DDR2_DQ21/DDR3_DQ21 DB DDR2 or DDR3 Data Bit 21
H1 HDMI_CKP AO HDMI Output Clock Pair+
H2 HDMI_CKN AO HDMI Output Clock Pair-
H3 HDMI_CEC AB HDMI Consumer Electronics Control
I2C0_SDA DB I
2
C 0 Serial Data Signal H4
GPIO62 DB General Purpose IO 62
H8 3.3V PWR Digital I/O Power 3.3V
H9 3.3V PWR Digital I/O Power 3.3V
H10 3.3V PWR Digital I/O Power 3.3V
H11 GND PWR Digital Ground
H12 GND PWR Digital Ground
H13 GND PWR Digital Ground
H17 DDR2_DQ31/DDR3_DQ28 DB DDR2 Data Bit 31 or DDR3 Data Bit 28
H18 DDR2_DQ24/DDR3_DQ24 DB DDR2 or DDR3 Data Bit 24
H19 DDR2_DQ23/DDR3_DQ17 DB DDR2 Data Bit 23 or DDR3 Data Bit 17
H20 DDR2_DQ16/DDR3_DQ19 DB DDR2 Data Bit 16 or DDR3 Data Bit 19
J1 HDMI_D0P AO HDMI Output Data Pair 0+
J2 HDMI_D0N AO HDMI Output Data Pair 0-
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Pin No. Pin Name I/O Description
J3 HDMI_GND GND HDMI Ground
I2C0_SCL DB I
2
C 0 Serial Clock Output J4
GPIO61 DB General Purpose IO 61
J8 GND PWR Digital Ground
J9 GND PWR Digital Ground
J10 GND PWR Digital Ground
J11 GND PWR Digital Ground
J12 GND PWR Digital Ground
J13 GND PWR Digital Ground
J17 DDR2/3_UUDQS DB DDR2 or DDR3 DQ[31:24] Data Strobe
J18 DDR2/3_UUDQS# DB DDR2 or DDR3 DQ[31:24] Data Strobe
J19 DDR2/3_ULDQS DB DDR2 or DDR3 DQ[23:16] Data Strobe
J20 DDR2/3_ULDQS# DB DDR2 or DDR3 DQ[23:16] Data Strobe
K1 HDMI_D1P AO HDMI Output Data Pair 1+
K2 HDMI_D1N AO HDMI Output Data Pair 1-
K3 HDMI_Vref PWR HDMI Reference Pin
K4 HDMI_3.3V PWR HDMI Power 3.3V
K8 1.0V PWR Core Power 1.0V
K9 1.0V PWR Core Power 1.0V
K10 1.0V PWR Core Power 1.0V
K11 1.0V PWR Core Power 1.0V
K12 1.0V PWR Core Power 1.0V
K13 1.0V PWR Core Power 1.0V
K17 DDR2/3_UUDM DO DDR2 or DDR3 DQ[31:24] Data Mask
K18 DDR2/3_ULDM DO DDR2 or DDR3 DQ[23:16] Data Mask
K19 DDR2_DQ17/DDR3_DQ18 DB DDR2 Data Bit 17 or DDR3 Data Bit 18
K20 DDR2_DQ22/DDR3_DQ16 DB DDR2 Data Bit 22 or DDR3 Data Bit 16
L1 HDMI_D2P AO HDMI Output Data Pair 2+
L2 HDMI_D2N AO HDMI Output Data Pair 2-
L3 HDMI_GND GND HDMI Ground
L4 HDMI_GND GND HDMI Ground
L8 1.0V PWR Core Power 1.0V
L9 1.0V PWR Core Power 1.0V
L10 1.0V PWR Core Power 1.0V
L11 1.0V PWR Core Power 1.0V
L12 1.0V PWR Core Power 1.0V
L13 1.0V PWR Core Power 1.0V
L17 DDR2_DQ25/DDR3_DQ29 DB DDR2 Data Bit 25 or DDR3 Data Bit 29
L18 DDR2_DQ30/DDR3_DQ31 DB DDR2 Data Bit 30 or DDR3 Data Bit 31
L19 DDR2_DQ20/DDR3_DQ20 DB DDR2 or DDR3 Data Bit 20
L20 DDR2_DQ19/DDR3_DQ22 DB DDR2 Data Bit 19 or DDR3 Data Bit 22
M1 ETN_TXON AO Ethernet 10/100Mbps Transmit Output Pair-
M2 ETN_TXOP AO Ethernet 10/100Mbps Transmit Output Pair+
M3 ETN_1.0V PWR Ethernet Power 1.0V
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Pin No. Pin Name I/O Description
M4 HDMI_HPD DI HDMI Hot Plug Detect
M8 GND PWR Digital Ground
M9 GND PWR Digital Ground
M10 GND PWR Digital Ground
M11 GND PWR Digital Ground
M12 GND PWR Digital Ground
M13 GND PWR Digital Ground
M17 DDR2_DQ28/DDR3_DQ27 DB DDR2 Data Bit 28 or DDR3 Data Bit 27
M18 DDR2_DQ27/DDR3_DQ25 DB DDR2 Data Bit 27 or DDR3 Data Bit 25
M19 DDR2_A7/DDR3_A7 DO DDR2 or DDR3 Address Bit 7
M20 DDR2_A12/DDR3_ODT DO DDR2 Address Bit 12 or DDR3 On-Die-Termination
N1 ETN_RXIN AI Ethernet 10/100Mbps Receive Input Pair-
N2 ETN_RXIP AI Ethernet 10/100Mbps Receive Input Pair+
N3 ETN_GND GND Ethernet Ground
N4 ETN_3.3V PWR Ethernet Power 3.3V
N8 GND PWR Digital Ground
N9 GND PWR Digital Ground
N10 GND PWR Digital Ground
N11 GND PWR Digital Ground
N12 1.8V/1.5V PWR DDR2 or DDR3 Power
N13 1.8V/1.5V PWR DDR2 or DDR3 Power
N17 1.8V/1.5V PWR DDR2 or DDR3 Power
N18 DDR3_RESET# DO DDR3 Reset
N19 DDR2_A3/DDR3_A13 DO DDR2 Address Bit 3 or DDR3 Address Bit 13
N20 DDR2_A9/DDR3_A9 DO DDR2 or DDR3 Address Bit 9
P1 USB0_DP AB USB 0 D+ Signal
P2 USB0_DM AB USB 0 D- Signal
P3 USB_1.0V PWR USB Power 1.0V
EJ0_TCK DI EJTAG Test Clock Input (Isolation Block)
IGPIO1 DB Isolation General Purpose IO 1
P4
USB0_OverCur_FLAG DI USB0 Over Current Power Detect
P17 DVRI PWR DDR2 or DDR3 Reference Voltage Input
P18 DDR2_A10/DDR3_A2 DO DDR2 Address Bit 10 or DDR3 Address Bit 2
P19 DDR2_A5/DDR3_A5 DO DDR2 or DDR3 Address Bit 5
P20 DDR2_A3-1/DDR3_A5-1 DO DDR2 Address Bit 3 for 2nd DDR2 Chip or DDR3 Address Bit 5 for
2nd DDR3 Chip
R1 USB1_DP AB USB 1 D+ Signal
R2 USB1_DM AB USB 1 D- Signal
R3 USB_GND GND USB Ground
R4 USB_3.3V PWR USB Power 3.3V
R17 DZQ DB DDR Calibration
R18 DDR2_BA1/DDR3_BA0 DO DDR2 Bank Address Bit 1 Output or DDR3 Bank Address Bit 0 Output
R19 DDR2_BA0/DDR3_A0 DO DDR2 Bank Address Bit 0 Output or DDR3 Address Bit 0
R20 DDR2_A1/DDR3_A3 DO DDR2 Address Bit 1 or DDR3 Address Bit 3
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Pin No. Pin Name I/O Description
T1 SATA_HSIP AI SATA RX Channel Positive Input
T2 SATA_HSIN AI SATA RX Channel Negative Input
T3 SATA_1.0V PWR SATA Power 1.0V
EJ0_TMS DI EJTAG Test Mode Select Input (Isolation Block)
IGPIO2 DB Isolation General Purpose IO 2
USB1_OverCur_FLAG DI USB1
In Host Mode: Over Current Power Detect
T4
USB1_VBUS DI USB1
In Device Mode: VBUS-In Detect
T17 GND PWR Digital Ground
T18 DDR2_WE#/DDR3_CS# DO DDR2 Write Enable Output or DDR3 Chip Select Output
T19 DDR2_A13/DDR3_CAS# DO DDR2 Address Bit 13 or DDR3 Column Address Select Output
T20 DDR2_BA2/DDR3_BA2 DO DDR2 or DDR3 Bank Address Bit 2 Output
U1 SATA_HSON AO SATA TX Channel Negative Output
U2 SATA_HSOP AO SATA TX Channel Positive Output
U3 SATA_GND GND SATA Ground
U4 GPIO89 DB General Purpose IO 89
U5 GPIO108 DB General Purpose IO 108
U6 GPIO112 DB General Purpose IO 112
U7 NAND_D3 DB NAND Flash Data Bit 3
NAND_D7 DB NAND Flash Data Bit 7 U8
SD_D[1] DB SD/MMC Data 1
U9 NAND_CE1# DO NAND Flash Chip Enable 1
NAND_ALE DO NAND Flash Address Latch Enable U10
SD_D[2] DB SD/MMC Data 2
U11 GND PWR Digital Ground
U12 DDR2_DQ11/DDR3_DQ9 DB DDR2 Data Bit 11 or DDR3 Data Bit 9
U13 DDR2_DQ14/DDR3_DQ15 DB DDR2 Data Bit 14 or DDR3 Data Bit 15
U14 DDR2/3_LLDM DO DDR2 or DDR3 DQ[7:0] Data Mask
U15 DDR2/3_LUDQS# DB DDR2 or DDR3 DQ[15:8] Data Strobe
U16 DDR2_DQ8/DDR3_DQ8 DB DDR2 Data Bit 8 or DDR3 Data Bit 8
U17 DDR2_DQ13/DDR3_DQ10 DB DDR2 Data Bit 13 or DDR3 Data Bit 10
U18 DDR2_CKE/DDR3_WE# DO DDR2 Clock Enable Output or DDR3 Write Enable Output
U19 DDR2_A8/DDR3_A11 DO DDR2 Address Bit 8 or DDR3 Address Bit 11
U20 DDR2_A11/DDR3_RAS# DO DDR2 Address Bit 11 or DDR3 Row Address Select Output
VFD_CLK DO VFD Controller Clock V1
IGPIO4 DB Isolation General Purpose IO 4
VFD_D DB VFD Controller Data Input/Output V2
IGPIO5 DB Isolation General Purpose IO 5
EJ0_TDO DO EJTAG Test Data Output V3
IGPIO7 DB Isolation General Purpose IO 7
NAND/ECC Select:
Pull high for 12-bit ECC NAND flash
Pull low for 6-bit NAND flash
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Pin No. Pin Name I/O Description
V4 GPIO90 DB General Purpose IO 90
V5 GPIO109 DB General Purpose IO 109
V6 NAND_D0 DB NAND Flash Data Bit 0
V7 NAND_D4 DB NAND Flash Data Bit 4
V8 NAND_RDY DI NAND Flash Ready
V9 SD_CLK DO SD/MMC Card Clock
NAND_CE3# DO NAND Flash Chip Enable 3 V10
SD_WP DI SD/MMC Write Protect
V11 GND PWR Digital Ground
V12 DDR2_DQ12/DDR3_DQ11 DB DDR2 Data Bit 12 or DDR3 Data Bit 11
V13 DDR2_DQ9/DDR3_DQ13 DB DDR2 Data Bit 9 or DDR3 Data Bit 13
V14 DDR2/3_LUDM DO DDR2 or DDR3 DQ[15:8] Data Mask
V15 DDR2/3_LUDQS DB DDR2 or DDR3 DQ[15:8] Data Strobe
V16 DDR2_DQ15/DDR3_DQ12 DB DDR2 Data Bit 15 or DDR3 Data Bit 12
V17 DDR2_DQ10/DDR3_DQ14 DB DDR2 Data Bit 10 or DDR3 Data Bit 14
V18 DDR2_A2/DDR3_A1 DO DDR2 Address Bit 2 or DDR3 Address Bit 1
V19 DDR2_A4/DDR3_A6 DO DDR2 Address Bit 4 or DDR3 Address Bit 6
V20 DDR2_A6/DDR3_A8 DO DDR2 Address Bit 6 or DDR3 Address Bit 8
VFD_CS# DO VFD Controller Chip Select W1
IGPIO3 DB Isolation General Purpose IO 3
W2 RESET# DI Chip Reset
EJ0_TDI DI EJTAG Test Data Input W3
IGPIO8 DB Isolation General Purpose IO 8
W4 GPIO106 DB General Purpose IO 106
W5 GPIO110 DB General Purpose IO 110
W6 NAND_D1 DB NAND Flash Data Bit 1
W7 NAND_D5 DB NAND Flash Data Bit 5
NAND_RD# DO NAND Flash Read Enable W8
SD_D[0] DB SD/MMC Data 0
W9 SD_CMD DB SD/MMC Card Command Line
W10 NAND_WR# DO DAND Flash Write Enable
W11 1.8V/1.5V PWR DDR2 or DDR3 Power
W12 DDR2_DQ3/DDR3_DQ6 DB DDR2 Data Bit 3 or DDR3 Data Bit 6
W13 DDR2_DQ6/DDR3_DQ0 DB DDR2 Data Bit 6 or DDR3 Data Bit 0
W14 DDR2/3_LLDQS# DB DDR2 or DDR3 DQ[7:0] Data Strobe
W15 DDR2_DQ0/DDR3_DQ3 DB DDR2 Data Bit 0 or DDR3 Data Bit 3
W16 DDR2_DQ5/DDR3_DQ5 DB DDR2 Data Bit 5 or DDR3 Data Bit 5
W17 DDR2/3_CK# DO DDR2 or DDR3 Inverse Clock Output
W18 DDR2_RAS#/DDR3_A10 DO DDR2 Row Address Select Output or DDR3 Address Bit 10
W19 DDR2_CAS#/DDR3_A12 DO DDR2 Column Address Select Output or DDR3 Address Bit 12
W20 DDR2_A2-1/DDR3_A4-1 DO DDR2 Address Bit 2 for 2nd DDR2 Chip or DDR3 Address Bit 4 for
2nd DDR3 Chip
IR_IN DI Infrared Input from IR Receiver Y1
IGPIO6 DB Isolation General Purpose IO 6
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Pin No. Pin Name I/O Description
STANDBY DO Standby Mode Enable Y2
IGPIO0 DB Isolation General Purpose IO 0
EJ0_RST# DI EJTAG Test Reset Input Y3
IGPIO9 DB Isolation General Purpose IO 9
Y4 GPIO107 DB General Purpose IO 107
Y5 GPIO111 DB General Purpose IO 111
Y6 NAND_D2 DB NAND Flash Data Bit 2
Y7 NAND_D6 DB NAND Flash Data Bit 6
Y8 NAND_CE0# DO NAND Flash Chip Enable 0
NAND_CLE DO DAND Flash Command Latch Enable Y9
SD_D[3] DB SD/MMC Data 3
NAND_CE2# DO NAND Flash Chip Enable 2 Y10
SD_CD DI SD/MMC Card Detect
Y11 1.8V/1.5V PWR DDR2 or DDR3 Power
Y12 DDR2_DQ4/DDR3_DQ4 DB DDR2 Data Bit 4 or DDR3 Data Bit 4
Y13 DDR2_DQ1/DDR3_DQ2 DB DDR2 Data Bit 1 or DDR3 Data Bit 2
Y14 DDR2/3_LLDQS DB DDR2 or DDR3 DQ[7:0] Data Strobe
Y15 DDR2_DQ7/DDR3_DQ1 DB DDR2 Data Bit 7 or DDR3 Data Bit 1
Y16 DDR2_DQ2/DDR3_DQ7 DB DDR2 Data Bit 2 or DDR3 Data Bit 7
Y17 DDR2/3_CK DO DDR2 or DDR3 Clock Output
Y18 DDR2_ODT/DDR3_CKE DO DDR2 On-Die-Termination or DDR3 Clock Enable Output
Y19 DDR2_CS#/DDR3_BA1 DO DDR2 Chip Select Output or DDR3 Bank Address Bit 1 Output
Y20 DDR2_A0/DDR3_A4 DO DDR2 Address Bit 0 or DDR3 Address Bit 4
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7. Licenses
Supply of this product does not convey a license under the relevant intellectual property of the companies
mentioned in this section nor imply any right to use this intellectual property in any finished end-user or
ready to use final product. An independent license for such use is required and can be obtained by
contacting the company or companies concerned.
Details of features requiring licenses are not provided in this datasheet. Features requiring licenses are:
DivX
DivX and the DivX logo are registered trademarks of DivXNet-works, Inc. in the USA and other
countries.
RM/RMVB
RM/RMVB is the intellectual property of RealNetworks. The RM/RMVB licenses allow the use of the
corresponding decoder executed in the RTD1185. For details, contact RealNetworks at: RealNetworks,
Attn: Helix Community Manager, 2601 Elliott Avenue, Seattle, WA 98121, USA.
http://www.realnetworks.com.
Dolby® Digital, Digital Plus, TrueHD, Pro Logic
® II
Dolby Digital, Digital Plus, TrueHD, and Pro Logic II are intellectual properties of Dolby Labs. The
Dolby Digital, Digital Plus, TrueHD, and Pro Logic II license allow the use of the corresponding decoder
embedded in the RTD1185.
For details, contact Dolby Labs at: Dolby Labs, 100 Potrero Avenue, San Francisco, CA 94103, USA.
DTS®
DTS is the intellectual property of Digital Theater Systems Inc. The DTS licenses allow the use of the
corresponding decoder executed in the RTD1185. For details, contact Digital Theater Systems Inc at:
DTS, 5171 Clareton Drive, Agoura Hills, CA 91301, USA. http://www.dtsonline.com.
Windows Media®
Windows Media is the intellectual property of Microsoft Corporation. The Windows Media license
allows the use of the Windows Media decoders in the RTD1185. For details, contact Microsoft at:
Microsoft Corporation, One Microsoft Way, Redmond, WA 98052-6399, USA.
http://www.microsoft.com.
Windows Media DRM
Windows Media DRM 10 for Network Devices allows the RTD1185 to play back Windows Media–based
protected content that resides on another computer on a network.
For details, contact Microsoft at: Microsoft Corporation, One Microsoft Way, Redmond, WA
98052-6399, USA. http://www.microsoft.com.
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8. System Global Resources
8.1. Power Supply
It is important to provide adequate power and ground for high-speed digital and sensitive analog design.
To achieve the best quality, power and ground pins are separated into several groups.
Table 2. Power Supply Specification
Power Min. Typ. Max. Unit Description
1.0V - 1.0 - V Power Supply of Core Digital Logic
1.0V - 1.0 - V Power Supply of Analog Logic
ISO_1.0V 1.05 1.05 - V Power Supply of Isolated Block Logic
1.8V - 1.8 - V Power Supply of SSTL18 I/O Pad
1.5V - 1.5 - V Power Supply of SSTL15 I/O Pad
3.3V - 3.3 - V Power Supply of I/O Pad or HW Block
RTC_3.3V 1.0 3.3 - V Power Supply of RTC Block
DVRI - 0.9 - V I/O Reference Voltage of SSTL18 Interface
DVRI - 0.75 - V I/O Reference Voltage of SSTL15 Interface
8.2. Power Management
The RTD1185 provides a Sleep Mode that shuts down all PLLs and logic to save power during idle state.
Sleep Mode is entered via a software instruction sequence, and exited by a hardware reset. External
wake-up events may be selected to automatically generate a wake-up reset.
For lower power consumption in Sleep Mode, all parts of the RTD1185 can be powered off except for the
isolation block. The wake-up function still works in this Sleep Mode.
Some RTD1185 modules could be individually powered down by gating off their clock tree. Those
modules can be powered on without resetting the whole chip.
8.3. Electrical Characteristics of LVTTL I/O Pads
Table 3. LVTTL Specification
Symbol Parameter Min. Typ. Max. Unit Condition
VIH HIGH Level Input Voltage 2.0 - - V -
VIL LOW Level Input Voltage - - 0.8 V -
VOH HIGH Level Output Voltage VCC-0.2 VCC - V -IO = 20µA
VOL LOW Level Output Voltage - - 0.4 V IO = 4.0mA
±II Input Leakage Current - 1 2 µA
VIN ≥ VIH or
VIN ≤ VIL
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8.4. Reset, Clock, and PLL
Table 4. System Global Resources External Pin Description
Pin Name IO Standard Type Description
RESET# LVTTL DI Chip Reset, Schmitt Trigger Input, Internal, Weakly Pulled-Up
XTLI Analog AI System Clock 27MHz
XTLO Analog AO System Clock 27MHz
REXT Analog AB Bandgap Voltage of Whole Chip, Connect to GND via a 15KΩ, ±1% Resistor
The external RESET# signal is low-active, Schmitt trigger input. To take effect, it must be held low for at
least 500ns. An external crystal (27MHz) is required for normal function, and the embedded PLL circuit
will generate all necessary clock signals for various modules. The crystal accuracy should be under
30ppm to ensure the best quality.
SSC (Spread Spectrum Clock) technology is a useful feature for system designers to solve the EMI
problem. For those modules that do not require fixed frequency, SSC has been used for a number of years
with very good results.
8.5. Thermal Considerations
To maintain a stable operating condition, the system designer should stay within maximum temperature
limits. The temperature of the chip case (center of top side) should not exceed 90°C in any condition.
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8.6. Power-On Sequence
Generally, the power-on sequence should be as follows:
• Apply 1.0V, 3.3V, and 1.5V or 1.8V
• Wait for supplies to stabilize
• Reset operation completes
• System boots up
The RTD1185 integrates a Power-On-Reset (POR) circuit to ensure the chip powers up in a default state.
It monitors the status of 3.3V and 1.0V. The POR circuit reset will release after 220
crystal clock cycles
when both VDD and VCORE are stable.
Figure 5. POR Circuit Diagram
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The Power-On-Reset (POR) will assert a reset signal when the 3.3V or 1.0V fall below certain voltage
levels. Refer to Figure 6, the sequence of applying 3.3V and 1.0V is suggested to be 1.0V leads 3.3V; that
is, t1 > 0.
1.8V or 1.5V is required to be stable before the end of the reset duration, that is, t2 > 0.
Figure 6. Power-On Sequence Timing Diagram
Table 5. POR Circuit Specification
Parameter Description TYP. Unit
3.3V_MIN Minimum Voltage to De-Assert POR 2.5 V
1.0V_MIN Minimum Voltage to De-Assert POR 0.8 V
3.3V_DROP Trigger Voltage to Assert POR 2.0 V
1.0V_DROP Trigger Voltage to Assert POR 0.75 V
tPOR POR Reset Time 220
Cycles
t1 Lead Time between 1.0V and 3.3V 2 mS
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8.7. System Boot Up Considerations
Once the reset signal is released, the RTD1185 will fetch instructions from the external Flash ROM
within 14 cycles. Before the first fetch operation, Flash ROM is required to be ready for reading. For
modern serial Flash ROM, it needs some time (tRH) to make itself ready for operation after
power-on/reset. In a typical system, there are two possible scenarios:
• Power-On Reset: The whole system is powered-on from a power-off state. Generally, the tPOR is about
38ms; this value is far greater than tRH, which is several micro seconds. In this condition, Flash ROM
is already operational before the first instruction fetch, so there is no issue.
• Hard Reset: The system is in power-on state and receives a reset signal from the RESET_N pin. If
Flash ROM could not be ready in 14 cycles, the system may malfunction due to an unknown
instruction being fetched. The system designer should carefully handle this issue to prevent
mysterious bugs. The rule of thumb is to keep t3 (refer to Figure 7) greater than tRH. One simple
approach is never to reset Flash ROM except via its own power-on-reset.
RESET_N /
CHIP_RESET
Flash RESET#
Flash CE# / OE#
t3
tRH = 14 cycles
Figure 7. System Reset and Flash Reset
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9. DDR2/3 Controller Unit
The RTD1185 DDR2/3 Controller Unit (DCU) provides memory control signals required for external
DDR2/DDR3 SDRAM access. With a 32-bit-wide DDR2/DDR3 SDRAM, the DCU can access up to
512MB.
9.1. Features
• Supports up to 512MB
• 1.8V SSTL18 compatible I/O for DDR2
• 1.5V SSTL15 compatible I/O for DDR3
9.2. DCU Block External Pin Description
Table 6. DCU Block External Pin Description
Pin Name IO Standard Type Description
DDR2/3_CK SSTL18/SSTL15 DO Clock (Differential Clock)
DDR2/3_CK# SSTL18/SSTL15 DO Inverse Clock (Differential Clock)
DDR2_CKE/DDR3_CKE SSTL18/SSTL15 DO Clock Enable
DDR2_ODT/DDR3_ODT SSTL18/SSTL15 DO On-Die Termination
DDR2_CS#/DDR3_CS# SSTL18/SSTL15 DO Chip Select
DDR2_RAS#/DDR3_RAS# SSTL18/SSTL15 DO Row Address Select
DDR2_CAS#/DDR3_CAS# SSTL18/SSTL15 DO Column Address Select
DDR2_WE#/DDR3_WE# SSTL18/SSTL15 DO Write Enable
DDR3_RESET# SSTL18/SSTL15 DO Reset (Only for DDR3)
DDR2/3_LLDQS SSTL18/SSTL15 DB DQ[7:0] Data Strobe (Differential Pair)
DDR2/3_LLDQS# SSTL18/SSTL15 DB Inverse DQ[7:0] Data Strobe (Differential Pair)
DDR2/3_LUDQS SSTL18/SSTL15 DB DQ[15:8] Data Strobe (Differential Pair)
DDR2/3_LUDQS# SSTL18/SSTL15 DB Inverse DQ[15:8] Data Strobe (Differential Pair)
DDR2/3_ULDQS SSTL18/SSTL15 DB DQ[23:16] Data Strobe (Differential Pair)
DDR2/3_ULDQS# SSTL18/SSTL15 DB Inverse DQ[23:16] Data Strobe (Differential Pair)
DDR2/3_UUDQS SSTL18/SSTL15 DB DQ[31:24] Data Strobe (Differential Pair)
DDR2/3_UUDQS# SSTL18/SSTL15 DB Inverse DQ[31:24] Data Strobe (Differential Pair)
DDR2/3_LLDM SSTL18/SSTL15 DO DQ[7:0] Data Mask
DDR2/3_LUDM SSTL18/SSTL15 DO DQ[15:8] Data Mask
DDR2/3_ULDM SSTL18/SSTL15 DO DQ[23:16] Data Mask
DDR2/3_UUDM SSTL18/SSTL15 DO DQ[31:24] Data Mask
DDR2_A[13:0]/DDR3_A[13:0] SSTL18/SSTL15 DO Address Bus
DDR2_BA[2:0]/DDR3_BA[2:0] SSTL18/SSTL15 DO Bank Address
DDR2_DQ[31:0]/DDR3_DQ[31:0] SSTL18/SSTL15 DB Data Bus
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9.3. SSTL18 Un-Terminated Output Load Example
In many applications where interconnections are short, there is no need for any termination.
Main Chip DDRII
VDDQ
VREF
DVRI
1.8V
0.9V
0.9V
DZQ
240/F
Figure 8. SSTL18 Un-Terminated Output Load Example
9.4. SSTL15 Un-Terminated Output Load Example
Main Chip DDRIII
VDDQ
VREF
DVRI
1.5V
0.75V
0.75V
DZQ
240/F
240/F
ZQ
Figure 9. SSTL15 Un-Terminated Output Load Example
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10. Flash Controller
The flash controller supports serial NOR flash memory and 8-bit NAND type flash memory. Each type
could be configured as boot device.
10.1. Feature
• Serial NOR Flash
ƒ Supports up to 16MB
ƒ Supports dual I/O read
ƒ Complies with MXIC protocol
• NAND Flash
ƒ Built-in SRAM buffer to improve performance
ƒ Built-in 6/12-bit ECC mechanism to enhance data reliability
ƒ Supports up to 4 flash chips with interleave accessing
10.2. Serial Flash Block External Pin Description
Table 7. Serial Flash Block External Pin Description
Pin Name IO Standard Type Description
SPI_CE# LVTTL DO Serial Flash Chip Select Output
SPI_SCK LVTTL DO Serial Flash Clock
SPI_SI/SIO0 LVTTL DB Serial Flash Data Input (for 1 x I/O)/
Serial Data Input & Output (for 2 x I/O read mode)
SPI_SO/SIO1 LVTTL DI Serial Flash Data Output (for 1 x I/O)/
Serial Data Input & Output (for 2 x I/O read mode)
10.3. NAND Flash Block External Pin Description
Table 8. NAND Flash Block External Pin Description
Pin Name IO Standard Type Description
NAND_CLE LVTTL DO NAND Flash Command Latch Enable
NAND_ALE LVTTL DO NAND Flash Address Latch Enable
NAND_RD# LVTTL DO NAND Flash Read Enable
NAND_WR# LVTTL DO NAND Flash Write Enable
NAND_RDY LVTTL DI NAND Flash Ready
NAND_CE[3:0]# LVTTL DO NAND Flash Chip Enable[3:0]
NAND_D[7:0] LVTTL DB NAND Flash Data[7:0]
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10.4. Flash Type Selection
Table 9. Flash Type Selection
N_FLASH Flash Type
1 8-Bit NAND Type Flash
0 Serial NOR Flash
10.5. Application Examples
Figure 10. Typical Application of Serial Flash
NAND_ALE
NAND_CLE
NAND_RD#
NAND_WR#
NAND_CE[3:0]#
NAND
Flash
N_FLASH
NAND_D[7:0]
NAND_RDY
3.3V
4.7K
3.3V
4.7K
VCC
GND
3.3V
0.1µ
4.7K
NAND_ALE
NAND_CLE
NAND_RD#
NAND_WR#
NAND_CE[3:0]#
NAND_D[7:0]
NAND_RDY
Figure 11. Typical Application of NAND Flash
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11. Peripherals
11.1. General Purpose I/O
The RTD1185 provides multiple GPIO pins. Each general purpose pin can be individually configured as
an input or output pin via the direction configuration register (refer to the separate RTD1185_GPIO.XLS
document). The Data output and input register (refer to the separate RTD1185_GPIO.XLS document) can
be used to control signals (high or low) when the GPIO pin is configured as output, and show the status
when the GPIO pin is configured as input.
When a GPIO pin is configured as input, it can also be configured as an interrupt generator (set in the
interrupt enable and detection polarity register) (refer to the separate RTD1185_GPIO.XLS document).
11.2. Universal Asynchronous Receiver and Transmitter
The RTD1185 provides two 16C550 compatible UARTs (Universal Asynchronous Receiver and
Transmitter).
11.2.1. Features
• UART CH0, 1 with 16-byte FIFO
• Programmable character properties, such as number of data bits per character (5~8), optional parity
bit (with odd or even select) and number of stop bits (1, 1.5, or 2)
• Interrupt output signal occurs whenever one of the several prioritized interrupt types are enabled and
active
• Receive Error
• Receive Data Available
• Character Timeout
• Transmitter Holding Register Empty at or below threshold
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11.2.2. UART Block External Pin Description
Table 10. UART Block External Pin Description
Pin Name IO Standard Type Description
UART0_RX LVTTL DI UART 0 Receive Data Input
UART0_TX LVTTL DO UART 0 Transmit Data Output
UART1_RX LVTTL DI UART 1 Receive Data Input
UART1_TX LVTTL DO UART 1 Transmit Data Output
11.2.3. Typical UART Application
Figure 12. Typical UART Application
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11.3. I
2
C Serial Interface
The RTD1185 can support two master/slave I
2
C-bus serial interfaces. A direct Serial Data Line (SDA)
and Serial Clock Line (SCL) carry information between bus master and peripheral devices that are
connected to the I
2
C-bus. The SDA and SCL lines are bi-directional.
11.3.1. Features
• Two-wire I
2
C serial interface
• Supports two speeds: Standard mode (100Kbps) and Fast mode (400Kbps)
• Clock synchronization
• Master or slave I
2
C operation
• Supports multi-Master operation (bus arbitration)
• 7-bit or 10-bit addressing
• 8-byte transmit and receive buffers
• 5V tolerance
11.3.2. I
2
C Block External Pin Description
Table 11. I
2
C Block External Pin Description
Pin Name IO Standard Type Description
I2C0_SCL LVTTL DB I
2
C Serial Clock Output
I2C0_SDA LVTTL DB I
2
C Serial Data Signal
I2C1_SCL LVTTL DB I
2
C Serial Clock Output
I2C1_SDA LVTTL DB I
2
C Serial Data Signal
11.3.3. Typical I
2
C Application
Figure 13. Typical I
2
C Application
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11.4. Infrared Receiver Controller
The RTD1185 Infrared Receiver controller is designed for receiving commands from consumer remote
controllers. It receives signals from an external IR receiver, translates signal zeros into data zeros, and
accumulates data bits that conform to the register setting requirements and buffers.
11.4.1. Features
• IR channel with 2 layers of 32-bit FIFO
• Supports length-coding protocol
• Supports phase-coding protocol
• Supports phase-width modulation
• Supports phase-distance modulation
• Address and command length up to 32 bits
• Supports RAW mode for software decode remote signal
11.4.2. IR Block External Pin Description
Table 12. IR Block External Pin Description
Pin Name IO Standard Type Description
IR_IN LVTTL DI Infrared Input from IR Receiver, 5V Tolerant
11.4.3. Typical IR Application
Main Chip
Infrared Receiver
Module (IRM)
IR_IN
3.3V
4.7K
Vout
0.1µ
3.3V
GND
VCC
Figure 14. Typical IR Application
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11.4.4. Verified Protocol
• NEC Protocol
ƒ Address and command are transmitted twice for reliability
ƒ Pulse distance modulation
ƒ Carrier frequency of 38kHz
ƒ Bit time of 1.12ms or 2.25ms
• Sony SIRC Protocol
ƒ Pulse width modulation
ƒ Carrier frequency of 40kHz
ƒ Bit time of 1.2ms or 0.6ms
• Philips RC-5 Protocol
ƒ Bi-phase coding
ƒ Carrier frequency of 36kHz
ƒ Constant bit time of 1.8ms
• Philips RC-6A Protocol (Mode 0 Only)
ƒ Bi-phase coding
ƒ Carrier frequency of 36kHz
ƒ Constant bit time of 888µs (except trailer bit)
• Sharp Protocol
ƒ Pulse distance modulation
ƒ Carrier frequency of 38kHz
ƒ Bit time of 1ms or 2ms
11.5. Timer Control
The RTD1185 provides three 32-bit timers, a 90kHz timer, and a watchdog timer. The 32-bit timer and
watchdog timer count at a fixed 27MHz rate. The 90kHz timer counts at 90kHz. The 32-bit timer can be
configured to timer mode or counter mode. Counter mode means the timer only times-out once. Hardware
will automatically disable timer interrupts after a time-out in counter mode. Software must enable the
timer interrupt and set the target value for the next usage.
11.5.1. Features
• Three sets of 32-bit timer hardware
• One 90kHz timer
• One watchdog timer
• 32-bit timer hardware can be configured to timer or counter mode
• Supports timer/counter pulse
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11.6. Real Time Clock
The Real Time Clock (RTC) can be operated by the backup battery while the system power is off. The
RTC data includes the time by half second, minute, hour, and date. The RTC works with an external
32.768kHz crystal and also can perform an alarm function.
11.6.1. Features
• Accepts 32.768kHz clock input
• Hex number data: Half-second, minute, hour, and date
• Programmable enable/disable half-second, minute, hour, date, and alarm interrupt
• Alarm function for system memory record
• RTC accuracy: 20ppm (under 60 seconds per month)
• Operating voltage: 1.0V up to 3.3V
• Low power consumption. Keeps correct time/data for up to 48 hours with a 0.022F gold cap
• Supports reset function
11.6.2. RTC Block External Pin Description
Table 13. RTC Block External Pin Description
Pin Name IO Standard Type Description
RTC_XI Analog AI Real-Time Clock 32.768kHz
RTC_XO Analog AO Real-Time Clock 32.768kHz
RTC_3.3V Power PWR Power for Real Time Clock
11.6.3. Typical RTC Application
Main Chip
RTC_XI RTC_XO
12pF 12pF
RTC_3.3V
GoldCap
3.3V
32.768KHz
Figure 15. Typical RTC Application
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11.7. Vacuum Fluorescent Display Interface
The RTD1185 provides a flexible serial interface to easily integrate with various VFD (Vacuum
Fluorescent Display) controllers currently available in the market.
11.7.1. Features
• Supports general VFD (Vacuum Fluorescent Display) controller function via serial interface
• Supports key-scan function and maximum 48 keypad
11.7.2. VFD Block External Pin Description
Table 14. VFD Block External Pin Description
Pin Name IO Standard Type Description
VFD_CLK LVTTL DO VFD Clock, Open-Drain
VFD_CS# LVTTL DO Data Enable, Open-Drain
VFD_D LVTTL DB Serial Data Input/Output, Open-Drain, 5V Tolerant
In Figure 16, all data transfer is related to the rising/falling of VFD_CLK. The LSB data bit is transferred
first. The VFD_D outputs serial data at the falling edge of the clock to ensure the external VFD controller
can latch the data at the rising edge of the clock. For data from the external VFD controller, VFD_D is
sampled at the rising edge of the clock. The VFD clock period could be set to either 1.037µs or 2µs.
Figure 16. VFD Serial Interface Timing
11.7.3. Typical VFD Application (PT6311)
Figure 17. Typical VFD Application (PT6311)
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12. TV Encoder
The TV encoder block encodes digital CR-Y-CB video data (4:2:2) to multiple standard TV signals, such
as NTSC, PAL CVBS, and component YUV or RGB output signals. Six 12-bit on-chip DACs provide
one composite video output, S-video, and three RGB or YPbPr component outputs. The Video output can
be formatted to be compatible with NTSC (M, J, 4.43), PAL (B, D, G, H, I, M, N, NC, 60), 525p, 625p,
720p, 1080i, and 1080p.
The video encoder also supports Wide-Screen Signaling (WSS), Copy Generation Management System
(CGMS), and Closed Caption (CC).
12.1. Features
• Six on-chip Digital-to-Analog Converters (DACs) with 12-bit resolution for composite output
(CVBS), and YPbPr or RGB component output
• Video encoding supports multi-composite format that includes NTSC[M, J, 4.43] and PAL [B, D, G,
H, I, M, N, NC, 60]
• Multi-format component supports interlaced YPbPr or RGB (525i/59.94Hz and 625i/50Hz) and
progressive YPbPr (525p/59.94Hz and 625p/50Hz) output
• Simultaneous composite and YPbPr outputs
• Supports HDTV YPbPr output (includes 1280×720 progressive and 1920×1080 interlaced)
• VBI encoding supports Closed Caption (CC) encoding, Wide-Screen Signaling (WSS), Video
Programming System (VPS), Teletext B for PAL, and Copy Generation Management System
(CGMS-A) for NTSC, 525p, 720p, 1080i, and 1080p
12.2. TV Encoder Analog Output Interface
Table 15. TV Encoder Analog Output Interface
Pin Name IO Standard Type Description
VDAC_A Analog AO Composite
VDAC_B Analog AO S-Video Y
VDAC_C Analog AO S-Video C
VDAC_D Analog AO Component Analog Video Green or Luminance
VDAC_E Analog AO Component Analog Video Blue or Pb
VDAC_F Analog AO Component Analog Video Red or Pr
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12.3. TV Encoder Application Examples
The RTD1185 incorporates an enhanced video encoder with six 12-bit video DACs that drive double
terminated 75Ω directly without external buffering. Figure 18 shows the video DAC output circuits.
Figure 18. Typical TV Encoder (Analog) Application Circuit
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13. HDMI
The RTD1185 incorporates a High Definition Multimedia Interface (HDMI) transmitter and a
full-function, single-link transmitter with High-bandwidth Digital Content Protection (HDCP). It
transmits studio-quality video/audio to any HDMI/DVI/HDCP-enabled digital receiver. This module is
fully compliant with the HDMI 1.3, DVI 1.0, and HDCP 1.1 specifications. The RTD1185 HDMI
transmitter can also carry control and status information.
13.1. Features
„ HDMI 1.3, HDCP 1.1, and DVI 1.0 compliant transmitter
‹ Video Support
ƒ Standard-definition video format timing:
1440 x 480i@59.94/60Hz, 1440 x 576i@50Hz, 720 x 480p@59.94/60Hz, 720 x 576p@50Hz
ƒ High-definition video format timing:
1280 x 720p@59.94/60Hz, 1280 x 720p@50Hz, 1920 x 1080i@59.94/60Hz, 1920 x
1080i@50Hz, 1920 x 1080p@24Hz, 1920 x 1080p@60Hz, 1920 x 1080p@50Hz
ƒ Pixel Encoding and Color Depth:
YCbCr 4:2:2 and Deep Color 24-bit
YCbCr 4:4:4 and Deep Color 24/30/36-bit
RGB 4:4:4 and Deep Color 24/30/36-bit
‹ Audio Support
ƒ Audio sample rate: 32~192k
ƒ Sample size: 16~24 bits
ƒ Up to 8-channel
ƒ Supports PCM, Dolby Digital, DTS digital audio transmission
ƒ IEC60958 and IEC61937 compatible
ƒ Supports High-Bit-Rate Audio
„ Master I
2
C interface for DDC connection
„ Supports Consumer Electronics Control (CEC)
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13.2. HDMI Block External Pin Description
Table 16. HDMI Block External Pin Description
Pin Name IO Standard I/O Description
HDMI_CKN Analog AO HDMI Output Clock Pair-
HDMI_CKP Analog AO HDMI Output Clock Pair+
HDMI_D0N Analog AO HDMI Output Data Pair 0-
HDMI_D0P Analog AO HDMI Output Data Pair 0+
HDMI_D1N Analog AO HDMI Output Data Pair 1-
HDMI_D1P Analog AO HDMI Output Data Pair 1+
HDMI_D2N Analog AO HDMI Output Data Pair 2-
HDMI_D2P Analog AO HDMI Output Data Pair 2+
HDMI_CEC Analog AB HDMI Consumer Electronics Control
HDMI_HPD LVTTL DI HDMI Hot Plug-In
13.3. Typical HDMI Transmitter Application Circuit
HDMI
Connector
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
5V
47K
2.2~
4.7k
HDMI_CKN
HDMI_CKP
Main Chip
HDMI_D0N
HDMI_D1N
HDMI_D2N
HDMI_D2P
HDMI_D1P
HDMI_D0P
HDMI_CEC
HDMI_HPD
I2C0_SCL
I2C0_SDA
5V
3.3V
27K
2.2~
4.7k
Figure 19. Typical HDMI Transmitter Application Circuit
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14. Audio Out Interface
The audio Out interface transfers audio PCM data or non-PCM bit-stream data. Two digital audio IO
interfaces, I
2
S and SPDIF, are supported. A 2-channel audio DAC (includes a 1Vrms line-level driver) is
embedded in this chip. For HDMI output, the RTD1185’s HDMI interface can send the PCM data from
Audio Out to the HDMI TX module.
14.1. Features
• Dolby Digital Consumer Decoder (5.1CH)
• Dolby Digital Prologic II
• Dolby Digital Plus
• Dolby Virtual Speaker
• Dolby Headphone
• Dolby TrueHD
• Dolby MAT Encoder
• Dolby Digital 5.1CH Encoder
• DTS (5.1CH)
• DTS HD
• DTS LBR
• DTS-ES
• DTS Encoder
• WMA (2CH)
• WMA Pro
• MPEG I Layer 1, 2, 3 (2CH)
• MPEG II Layer 1, 2
• MPEG4 HE AACv2
• AAC
• OGG
• RA1/RA-cook/RA-lossless
• LPCM/ADPCM
• CDDA
• FLAC
• Post Processing: SRS TruSurround XT, SRS
WOW HD, Sound Field Effect, Equalizer,
Depop, resampling, fade-in, fade-out,
Karaoke, Keyshift, BBE
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