25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Description This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM lo

文件：418.77 Kbytes 页数：17 Pages

IDT

25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Description This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM lo

文件：418.77 Kbytes 页数：17 Pages

IDT

25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Renesas

瑞萨

1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM

文件：157.04 Kbytes 页数：29 Pages

PHI

飞利浦

1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM

文件：157.04 Kbytes 页数：29 Pages

PHI

飞利浦

1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM

文件：157.04 Kbytes 页数：29 Pages

PHI

飞利浦