1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM

文件：157.04 Kbytes 页数：29 Pages

PHI

PHI

1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM

恩XP

1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM

文件：157.04 Kbytes 页数：29 Pages

PHI

PHI

25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Description This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM lo

文件：422.3 Kbytes 页数：17 Pages

IDT

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Features • 28-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on CSGateEN and RESET inputs • Low voltage operation: VDD = 1.7V to 1.9V • Available in 160-ball LFBGA package Applic

文件：676.61 Kbytes 页数：17 Pages

RENESAS

瑞萨

25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

Description This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM lo

文件：422.3 Kbytes 页数：17 Pages

IDT