ICSSSTUAF32865A中文资料瑞萨数据手册PDF规格书

特性 Features

• 28-bit 1:2 registered buffer with parity check functionality

• Supports SSTL_18 JEDEC specification on data inputs

and outputs

• Supports LVCMOS switching levels on CSGateEN and

RESET inputs

• Low voltage operation: VDD = 1.7V to 1.9V

• Available in 160-ball LFBGA package

Applications

• DDR2 Memory Modules

• Provides complete DDR DIMM solution with

ICS98ULPA877A or IDTCSPUA877A

• Ideal for DDR2 400, 533, and 667