HDTV AUDIO/VIDEO CLOCK SOURCE

Description The ICS662-03 provides synchronous clock generation for audio sampling clock rates derived from an HDTV stream. The device uses the latest PLL technology to provide superior phase noise and long term jitter performance. The device also supports a 27 MHz output clock for video MPEG app

文件：171 Kbytes 页数：7 Pages

IDT

NTSC/PAL AUDIO CLOCK

Description The ICS662-02 is a low cost, low jitter, high performance PLL clock synthesizer designed to replace oscillators and PLL circuits in set-top box and multimedia systems. Using ICS’ patented analog Phase Locked Loop (PLL) techniques, the device uses a NTSC/PAL reference clock input to pr

文件：95.35 Kbytes 页数：6 Pages

ICST

NTSC/PAL AUDIO CLOCK

Description The ICS662-02 is a low cost, low jitter, high performance PLL clock synthesizer designed to replace oscillators and PLL circuits in set-top box and multimedia systems. Using ICS’ patented analog Phase Locked Loop (PLL) techniques, the device uses a NTSC/PAL reference clock input to pr

文件：95.35 Kbytes 页数：6 Pages

ICST

HDTV AUDIO/VIDEO CLOCK SOURCE

Description The ICS662-03 provides synchronous clock generation for audio sampling clock rates derived from an HDTV stream. The device uses the latest PLL technology to provide superior phase noise and long term jitter performance. The device also supports a 27 MHz output clock for video MPEG app

文件：171 Kbytes 页数：7 Pages

IDT

HDTV AUDIO/VIDEO CLOCK SOURCE

Description The ICS662-03 provides synchronous clock generation for audio sampling clock rates derived from an HDTV stream. The device uses the latest PLL technology to provide superior phase noise and long term jitter performance. The device also supports a 27 MHz output clock for video MPEG app

文件：171 Kbytes 页数：7 Pages

IDT

HDTV AUDIO/VIDEO CLOCK SOURCE

Description The ICS662-03 provides synchronous clock generation for audio sampling clock rates derived from an HDTV stream. The device uses the latest PLL technology to provide superior phase noise and long term jitter performance. The device also supports a 27 MHz output clock for video MPEG app

文件：171 Kbytes 页数：7 Pages

IDT

HDTV AUDIO/VIDEO CLOCK SOURCE

Description The ICS662-03 provides synchronous clock generation for audio sampling clock rates derived from an HDTV stream. The device uses the latest PLL technology to provide superior phase noise and long term jitter performance. The device also supports a 27 MHz output clock for video MPEG app

文件：171 Kbytes 页数：7 Pages

IDT

PLL BUILDING BLOCK Phase detector and VCO blocks can be used Lower power CMOS process

Description The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO) and an output buffer. Through the use of external reference and VCO dividers (implemented wi

文件：218.91 Kbytes 页数：8 Pages

IDT

PLL BUILDING BLOCK

Description The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO) and an output buffer. Through the use of external reference and VCO dividers (implemented

文件：146.83 Kbytes 页数：7 Pages

ICST

PLL BUILDING BLOCK

Description The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO) and an output buffer. Through the use of external reference and VCO dividers (implemented

文件：146.83 Kbytes 页数：7 Pages

ICST