Package：16-SOIC（0.154"，3.90mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC DELAY BUFFER QUADRACLK 16SOIC

Renesas Electronics America Inc

QuadraClock??Quadrature Delay Buffer

Description The ICS672-01 and ICS672-02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals. Based on ICS’ proprietary low jitter Phase Locked Loop (PLL) techniques, each device provides five low skew outputs, with clock rates up to 84 MHz for the ICS6

文件：73.76 Kbytes 页数：5 Pages

ICST

QUADRACLOCK QUADRATURE DELAY BUFFER

Features • Packaged in 16-pin SOIC • Pb (lead) free package, RoHS compliant • Input clock range from 5 MHz to 150 MHz (depends on multiplier) • Clock outputs from up to 84 MHz (ICS672-01) and up to 135 MHz (ICS672-02) • Zero input-output delay • Integrated x0.5, x1, x2, x3, x4, x5, or x6 s

文件：260.76 Kbytes 页数：8 Pages

RENESAS

瑞萨

QUADRACLOCK QUADRATURE DELAY BUFFER

Features • Packaged in 16-pin SOIC • Pb (lead) free package, RoHS compliant • Input clock range from 5 MHz to 150 MHz (depends on multiplier) • Clock outputs from up to 84 MHz (ICS672-01) and up to 135 MHz (ICS672-02) • Zero input-output delay • Integrated x0.5, x1, x2, x3, x4, x5, or x6 s

文件：260.76 Kbytes 页数：8 Pages

RENESAS

瑞萨

QuadraClock??Quadrature Delay Buffer

Description The ICS672-01 and ICS672-02 are zero delay buffers that generate four output clocks whose phases are spaced at 90° intervals. Based on ICS’ proprietary low jitter Phase Locked Loop (PLL) techniques, each device provides five low skew outputs, with clock rates up to 84 MHz for the ICS6

文件：73.76 Kbytes 页数：5 Pages

ICST