12-stage binary ripple counter

1. General description The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and

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12-stage binary ripple counter

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12-stage binary ripple counter

The HEF4040B-Q100 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW • Automotive product qualification in accordance with AEC-Q100 (Grade 3)• Specified from -40 °C to +85 °C\n\n• Tolerant of slow clock rise and fall time\n• Fully static operation\n• 5 V, 10 V and 15 V parametric ratings\n• Standardized symmetrical output characteristics\n• ESD protection:• MIL-STD-8;

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Package：16-SOIC（0.154"，3.90mm 宽）；包装：管件 类别：集成电路（IC） 计数器，除法器 描述：IC RIPPLE COUNTER 12ST 16SOIC

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