Quadruple D-type flip-flop

DESCRIPTION The HEF40175B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (O0 to O3), and four complementary buffered outputs (O0 to O3). Information on D0 to D3 is trans

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PHI

飞利浦

Quad D-type flip-flop

1. General description The HEF40175B is a quad positive edge triggered D-type flip-flop with four data (Dn) inputs, common clock (CP) and asynchronous master reset (MR) inputs, and complementary Qn and Qn outputs. When MR is HIGH data at the D-input that meets the set-up and hold time requireme

文件：238.1 Kbytes 页数：13 Pages

NEXPERIA

安世

Quad D-type flip-flop Complies with JEDEC standard JESD 13-B

文件：152.33 Kbytes 页数：15 Pages

恩XP

Quad D-type flip-flop

1. General description The HEF40175B is a quad positive edge triggered D-type flip-flop with four data (Dn) inputs, common clock (CP) and asynchronous master reset (MR) inputs, and complementary Qn and Qn outputs. When MR is HIGH data at the D-input that meets the set-up and hold time requireme

文件：238.1 Kbytes 页数：13 Pages

NEXPERIA

安世

Quad D-type flip-flop Complies with JEDEC standard JESD 13-B

文件：152.33 Kbytes 页数：15 Pages

恩XP

Quad D-type flip-flop

The HEF40175B is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (Q0 to Q3), and four complementary buffered outputs (Q0 to Q3). Information on D0 to D3 is transferred to Q0 to Q3 o • Fully static operation\n• 5 V, 10 V, and 15 V parametric ratings\n• Standardized symmetrical output characteristics\n• Specified from –40 ℃ to +125 ℃\n• Complies with JEDEC standard JESD 13-B;

Nexperia

安世

Quad D-type flip-flop

The HEF40175B is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP), an overriding asynchronous master reset input (MR), four buffered outputs (Q0 to Q3), and four complementary buffered outputs (Q0 to Q3). Information on D0 to D3 is transferred to Q0 to Q3 o • Fully static operation\n• 5 V, 10 V, and 15 V parametric ratings\n• Standardized symmetrical output characteristics\n• Specified from –40 ℃ to +125 ℃\n• Complies with JEDEC standard JESD 13-B;

Nexperia

安世

Quad D-type flip-flop

The HEF40175B-Q100 is a quad positive edge triggered D-type flip-flop with four data (Dn) inputs, common clock (CP) and asynchronous master reset (MR) inputs, and complementary Qn and Qn outputs. When MR is HIGH data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Wide supply voltage range from 3.0 V to 15.0 V\n• CMOS low power dissipation\n• High noise immunity\n• Fully static operation\n• 5 V, 10 V, and 15 V parametric ra;

Nexperia

安世

Package：16-SOIC（0.154"，3.90mm 宽）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 4BIT 16SO

Nexperia USA Inc.

Package：16-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 4BIT 16SO

Nexperia USA Inc.